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1. 发明申请

US20120221916A1 MEMORY ARRAY ERROR CORRECTION APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：存储器阵列错误校正装置，系统和方法
公开(公告)号：US20120221916A1
公开(公告)日：2012-08-30
申请号：US13467699
申请日：2012-05-09
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

2. 发明授权

US07945840B2 Memory array error correction apparatus, systems, and methods 有权
标题翻译：存储器阵列纠错装置，系统和方法
公开(公告)号：US07945840B2
公开(公告)日：2011-05-17
申请号：US11705190
申请日：2007-02-12
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

3. 发明授权

US07200052B2 Apparatus and methods for regulated voltage 有权
标题翻译：用于调节电压的装置和方法
公开(公告)号：US07200052B2
公开(公告)日：2007-04-03
申请号：US11059136
申请日：2005-02-15
申请人： John F Schreck
发明人： John F Schreck
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G05F1/46 , G05F1/618 , G11C11/4074
摘要： An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.
摘要翻译：根据本发明的各个方面的电子系统包括具有调节输出以提供所选电压电平的存储器和电源调节电路。在一个实施例中，电源调节电路包括与电源连接并被配置为接收第一电压和第二电压并提供参考电压的参考电压电路和连接到参考电压的控制电路，并被配置为根据到参考电压。供电调节电路还包括由控制电路控制并被配置为根据参考电压调节调节电压的调节电路。电源调节电路还可以包括补偿电路，以对调节的电压提供额外的调整。

4. 发明授权

US5835395A Eprom pinout option 失效
标题翻译： Eprom引脚排列选项
公开(公告)号：US5835395A
公开(公告)日：1998-11-10
申请号：US82436
申请日：1993-06-28
申请人： John F. Schreck , Richard A. Bussey
发明人： John F. Schreck , Richard A. Bussey
IPC分类号： G11C5/00 , G11C7/10 , H01L23/50 , H01L21/90
CPC分类号： H01L23/50 , G11C7/1045 , H01L2924/0002
摘要： A memory device is presented having the option, using simple means, of using one basic chip for different pin-outs or chip configurations. The metal and pin-out option implementation are formed by: 1) a dual-function pad and associated circuitry with an option for either an Input/Output or an Input-only configuration and 2) rotation of the chip with respect to the orientation of the DIP (dual in-line package). The implementation of this invention has decreased area requirements and better performance capabilities than those of known prior-art implementations.
摘要翻译：提出了一种使用简单的手段，使用一个基本芯片用于不同引脚或芯片配置的存储器件。金属和引脚选择实现通过以下方式形成：1）双功能焊盘和相关电路，其具有用于输入/输出或仅输入配置的选项，以及2）芯片相对于 DIP（双列直插式封装）。本发明的实现与已知的现有技术实施方式相比，具有降低的面积要求和更好的性能。

5. 发明授权

US5491658A Column decoder for virtual ground memory array 失效
标题翻译：用于虚拟接地存储器阵列的列解码器
公开(公告)号：US5491658A
公开(公告)日：1996-02-13
申请号：US655566
申请日：1991-02-13
申请人： John F. Schreck , Phat C. Truong
发明人： John F. Schreck , Phat C. Truong
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C16/06 , G11C16/08 , G11C17/00
CPC分类号： G11C16/08 , G11C8/10 , G11C8/12
摘要： A virtual ground memory includes an array of rows and columns of memory cells and a plurality of alternating first and second column lines. The cells in each column are coupled to a first column line and a second column line. A first decoder selects a plurality of first column lines in response to first decoded address signals and selects one of the selected plurality of first column lines in response to second decoded address signals.
摘要翻译：虚拟接地存储器包括存储器单元的行和列的阵列以及多个交替的第一和第二列线。每列中的单元被耦合到第一列线和第二列线。第一解码器响应于第一解码地址信号选择多个第一列线，并且响应于第二解码地址信号选择所选择的多个第一列线中的一个。

6. 发明授权

US5313427A EEPROM array with narrow margin of voltage thresholds after erase 失效
标题翻译：擦除后具有电压阈值边缘窄的EEPROM阵列
公开(公告)号：US5313427A
公开(公告)日：1994-05-17
申请号：US763105
申请日：1991-09-20
申请人： John F. Schreck , David J. McElroy , Pradeep L. Shah
发明人： John F. Schreck , David J. McElroy , Pradeep L. Shah
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/16 , H01L27/115 , G11C16/06 , G11C11/34
CPC分类号： G11C16/16
摘要： A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.
摘要翻译：非易失性存储器具有成对的单元，其中每个单元包括控制栅极，浮置栅极和源极/漏极扩散。每对中的第一个单元可以产生一个浮动栅扩散电容的值。每对中的第二单元可以产生具有不同于第一值的扩散电容的浮置栅极的第二值。存储器包括用于将第一擦除脉冲施加到控制栅极的第一电路和对的第一单元的扩散，并且包括用于将第二擦除脉冲施加到控制栅极的第二电路和第二电路的扩散对。第一擦除脉冲可调整以具有与第二擦除脉冲不同的幅度，以便缩小擦除阈值电压的余量，从而补偿未对准。

7. 发明授权

US5287315A Skewed reference to improve ones and zeros in EPROM arrays 失效
标题翻译：倾斜的参考，以提高EPROM阵列中的零和零
公开(公告)号：US5287315A
公开(公告)日：1994-02-15
申请号：US057435
申请日：1993-05-07
申请人： John F. Schreck , Debra J. Dolby , David J. McElroy , Eddie H. Breashears , John H. MacPeak
发明人： John F. Schreck , Debra J. Dolby , David J. McElroy , Eddie H. Breashears , John H. MacPeak
IPC分类号： G11C16/28 , G11C29/00 , G11C7/02 , G11C11/34
CPC分类号： G11C29/78 , G11C16/28
摘要： A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for "ones" at low control gate voltage Vcc and for "zeros" at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.
摘要翻译：公开了一种用于改善非易失性存储器的检测边缘的结构和方法。通过改善在低控制栅极电压Vcc下的“一个”和在高控制栅极电压Vcc下的“零”的裕度来实现对非易失性存储器的感测边缘的改进。在低控制栅极电压Vcc下的感测改善通过使参考存储器单元的沟道长度形成具有比阵列的存储单元更长的沟道长度的方式来使读出放大器响应特性偏斜来实现。

8. 发明授权

US5182726A Circuit and method for discharging a memory array 失效
标题翻译：用于放电存储器阵列的电路和方法
公开(公告)号：US5182726A
公开(公告)日：1993-01-26
申请号：US645078
申请日：1991-01-23
申请人： John F. Schreck , Phat C. Truong
发明人： John F. Schreck , Phat C. Truong
IPC分类号： G11C7/12 , G11C16/26
CPC分类号： G11C7/12 , G11C16/26
摘要： A circuit and method for rapid removal of drain-column programming voltages from drain-column lines of a memory array. The circuit includes a resistor/transistor connected between a supply voltage and a common node, the resistor/transistor being enabled by a program enable signal. During the discharge operation, the source-drain paths of a driver transistors of the array connect column lines to reference potential. The gates of the driver transistors are coupled to the common node. An enabling transistor has a source-drain path connecting reference potential to the common node and has a gate connected to the program enable signal. The circuit includes at least one inverter, an OR circuit, and a bypass transistor. The bypass transistor has a source-drain path connected between the supply voltage and the common node and a gate coupled to the common node through the inverter and the OR circuit. The common node may be coupled to the gate of the driver transistor by a coupling transistor having a source-drain path connected between the common node and the gate of the driver transistor and a gate connected to a virtual ground signal.
摘要翻译：一种用于从存储器阵列的排列列线路快速去除排列编程电压的电路和方法。电路包括连接在电源电压和公共节点之间的电阻/晶体管，电阻/晶体管由程序使能信号使能。在放电操作期间，阵列的驱动器晶体管的源极 - 漏极路径将列线连接到参考电位。驱动器晶体管的栅极耦合到公共节点。启用晶体管具有将参考电位连接到公共节点的源极 - 漏极路径，并且具有连接到编程使能信号的栅极。该电路包括至少一个反相器，或电路和旁路晶体管。旁路晶体管具有连接在电源电压和公共节点之间的源极 - 漏极路径，以及通过反相器和OR电路耦合到公共节点的栅极。公共节点可以通过耦合晶体管耦合到驱动晶体管的栅极，耦合晶体管具有连接在驱动晶体管的公共节点和栅极之间的源极 - 漏极路径，以及连接到虚拟接地信号的栅极。

9. 发明授权

US5170077A Voltage level detecting circuit 失效
标题翻译：电压电平检测电路
公开(公告)号：US5170077A
公开(公告)日：1992-12-08
申请号：US583619
申请日：1990-09-14
申请人： John F. Schreck
发明人： John F. Schreck
IPC分类号： G01R19/165 , H03K17/30
CPC分类号： G01R19/16519 , H03K17/302
摘要： A voltage level detecting circuit is presented having simplistic construction, stable circuit operation and few components. The circuit includes: a p-channel transistor; a resistor; a ground terminal; a first voltage supply terminal for receiving a fixed voltage level; a second voltage supply terminal for receiving a variable voltage level; and an output terminal.
摘要翻译：电压电平检测电路具有结构简单，电路运行稳定，部件少的特点。该电路包括：p沟道晶体管; 一个电阻; 地面终端; 用于接收固定电压电平的第一电压供给端子; 用于接收可变电压电平的第二电压供给端子; 和输出端子。

10. 发明授权

US5132933A Bias circuitry for nonvolatile memory array 失效
标题翻译：用于非易失性存储器阵列的偏置电路
公开(公告)号：US5132933A
公开(公告)日：1992-07-21
申请号：US631606
申请日：1990-12-21
申请人： John F. Schreck , Shailesh R. Kadakia , Phat C. Truong
发明人： John F. Schreck , Shailesh R. Kadakia , Phat C. Truong
IPC分类号： G11C17/00 , G11C7/12 , G11C16/04 , G11C16/06 , G11C16/26
CPC分类号： G11C7/12 , G11C16/26
摘要： A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline. The circuit includes a common node; a resistor means coupled between the common node and each of the source- and drain-column lines; a drain-select means coupled to each drain-column line for transmitting, during a read cycle, a first preselected bias voltage lower than a supply voltage to the selected drain-column line; a source-select means coupled to each source-column line for transmitting, during the read cycle, a second preselected bias voltage to the one non-selected source-column line, the one non-selected source-column line coupled to a cell sharing the selected drain-column line and the selected wordline; and reference-select means for connecting, during the read cycle, the source-column lines, except the one non-selected source-column line, to reference potential. The sense amplifier and the driver circuit each include at least three transistors and have outputs coupled to drain-column lines and source-column lines, respectively, of the memory array.
摘要翻译：一种偏置电路，用于读取半导体存储器单元阵列的选定单元，其中每个单元耦合到漏 - 列线，源列线和字线，所选择的单元耦合到选定的漏 - 列线，选择的源列行和选定的字线。该电路包括一个公共节点; 耦合在公共节点和源极 - 漏极列线路中的每一个之间的电阻器件; 耦合到每个漏 - 列线的漏极选择装置，用于在读周期期间将低于供给电压的第一预选偏压电压传送到所选择的漏 - 列线; 耦合到每个源极列线的源极选择装置，用于在读取周期期间将第二预选偏置电压发送到所述一个未选择的源极列线，所述一个未选择的源极线耦合到一个小区共享所选择的排列列线和所选择的字线; 以及参考选择装置，用于在读取周期期间将除了一个未选择的源列线之外的源极列线连接到参考电位。读出放大器和驱动电路各自包括至少三个晶体管，并且具有分别耦合到存储器阵列的漏 - 列线和源 - 列线的输出。

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