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1. 发明授权

US09578727B2 Digital controller for an electronic ballast 有权
标题翻译：电子镇流器的数字控制器
公开(公告)号：US09578727B2
公开(公告)日：2017-02-21
申请号：US14174549
申请日：2014-02-06
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B37/02 , H05B41/282 , H05B41/392
CPC分类号： H05B41/2824 , H05B41/3927 , Y02B20/186
摘要： Provided are circuits and methods for a digital controller for an electronic ballast for a fluorescent lamp, comprising a feed-forward loop that provides information about a voltage firing angle, and a pulse width modulator that controls a duty ratio of at least one power switch of the electronic ballast according to the information. The digital controller may include a duty ratio controller implemented in the pulse width modulator. The digital controller may include one or more functions such as dimming, maintaining high power factor throughout the dimming range, low lamp power detection, lamp soft-start, and DC-link capacitor over-voltage detection for end of life protection or lamp failure protection. In one embodiment the ballast is a single stage, single switch ballast.
摘要翻译：提供了一种用于荧光灯电子镇流器的数字控制器的电路和方法，包括提供关于电压触发角度的信息的前馈环路和控制至少一个电源开关的占空比的脉宽调制器电子镇流器根据信息。数字控制器可以包括在脉冲宽度调制器中实现的占空比控制器。数字控制器可以包括一个或多个功能，例如调光，在整个调光范围内保持高功率因数，低灯功率检测，灯软启动和用于寿命终止保护或灯故障保护的DC链路电容器过电压检测。在一个实施例中，镇流器是单级单开关镇流器。

2. 发明授权

US08212492B2 Electronic ballast with high power factor 有权
标题翻译：电子镇流器具有高功率因数
公开(公告)号：US08212492B2
公开(公告)日：2012-07-03
申请号：US12457518
申请日：2009-06-12
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B41/16
CPC分类号： H05B41/28 , H05B41/2822 , H05B41/3927 , Y02B20/19
摘要： This invention provides an electronic ballast for a fluorescent lamp, including a rectifier for converting an alternating current input voltage into a direct current output voltage, and a circuit including a combined power factor correction (PFC) stage and an inverter, wherein the PFC stage and the inverter share a switch. Also provided is a controller for an electronic ballast, including a duty ratio controller that controls a duty ratio of a switch of the ballast, and means for adjusting the duty ratio according to a nonlinear function, so that an arc is sustained across the lamp. The controller and the ballast allow dimming of the fluorescent lamp while maintaining a high power factor.
摘要翻译：本发明提供了一种用于荧光灯的电子镇流器，包括用于将交流输入电压转换成直流输出电压的整流器，以及包括组合功率因数校正（PFC）级和逆变器的电路，其中PFC级和变频器共用开关。还提供了一种用于电子镇流器的控制器，包括控制镇流器开关的占空比的占空比控制器，以及根据非线性函数调整占空比的装置，使得电弧在整个灯上得以维持。控制器和镇流器允许荧光灯调光，同时保持高功率因数。

3. 发明授权

US09049773B2 Digital controller for an electronic ballast 有权
标题翻译：电子镇流器的数字控制器
公开(公告)号：US09049773B2
公开(公告)日：2015-06-02
申请号：US13459562
申请日：2012-04-30
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B37/02 , H05B41/282 , H05B41/392
CPC分类号： H05B41/2824 , H05B41/3927 , Y02B20/186
摘要： Provided are circuits and methods for a digital controller for an electronic ballast for a fluorescent lamp, comprising a feed-forward loop that provides information about a voltage firing angle, and a pulse width modulator that controls a duty ratio of at least one power switch of the electronic ballast according to the information. The digital controller may include a duty ratio controller implemented in the pulse width modulator. The digital controller may include one or more functions such as dimming, maintaining high power factor throughout the dimming range, low lamp power detection, lamp soft-start, and DC-link capacitor over-voltage detection for end of life protection or lamp failure protection. In one embodiment the ballast is a single stage, single switch ballast.
摘要翻译：提供了一种用于荧光灯电子镇流器的数字控制器的电路和方法，包括提供关于电压触发角度的信息的前馈环路和控制至少一个电源开关的占空比的脉宽调制器电子镇流器根据信息。数字控制器可以包括在脉冲宽度调制器中实现的占空比控制器。数字控制器可以包括一个或多个功能，例如调光，在整个调光范围内维持高功率因数，低灯功率检测，灯软启动和用于寿命终止保护或灯故障保护的直流链路电容器过电压检测。在一个实施例中，镇流器是单级单开关镇流器。

4. 发明申请

US20120306400A1 Digital Controller for an Electronic Ballast 有权
标题翻译：电子镇流器数字控制器
公开(公告)号：US20120306400A1
公开(公告)日：2012-12-06
申请号：US13459562
申请日：2012-04-30
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B41/38
CPC分类号： H05B41/2824 , H05B41/3927 , Y02B20/186
摘要： Provided are circuits and methods for a digital controller for an electronic ballast for a fluorescent lamp, comprising a feed-forward loop that provides information about a voltage firing angle, and a pulse width modulator that controls a duty ratio of at least one power switch of the electronic ballast according to the information. The digital controller may include a duty ratio controller implemented in the pulse width modulator. The digital controller may include one or more functions such as dimming, maintaining high power factor throughout the dimming range, low lamp power detection, lamp soft-start, and DC-link capacitor over-voltage detection for end of life protection or lamp failure protection. In one embodiment the ballast is a single stage, single switch ballast.
摘要翻译：提供了一种用于荧光灯电子镇流器的数字控制器的电路和方法，包括提供关于电压触发角度的信息的前馈环路和控制至少一个电源开关的占空比的脉宽调制器电子镇流器根据信息。数字控制器可以包括在脉冲宽度调制器中实现的占空比控制器。数字控制器可以包括一个或多个功能，例如调光，在整个调光范围内保持高功率因数，低灯功率检测，灯软启动和用于寿命终止保护或灯故障保护的直流链路电容器过电压检测。在一个实施例中，镇流器是单级单开关镇流器。

5. 发明申请

US20100039038A1 Electronic ballast with high power factor 有权
标题翻译：电子镇流器具有高功率因数
公开(公告)号：US20100039038A1
公开(公告)日：2010-02-18
申请号：US12457518
申请日：2009-06-12
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B41/36
CPC分类号： H05B41/28 , H05B41/2822 , H05B41/3927 , Y02B20/19
摘要： This invention provides an electronic ballast for a fluorescent lamp, including a rectifier for converting an alternating current input voltage into a direct current output voltage, and a circuit including a combined power factor correction (PFC) stage and an inverter, wherein the PFC stage and the inverter share a switch. Also provided is a controller for an electronic ballast, including a duty ratio controller that controls a duty ratio of a switch of the ballast, and means for adjusting the duty ratio according to a nonlinear function, so that an arc is sustained across the lamp. The controller and the ballast allow dimming of the fluorescent lamp while maintaining a high power factor.
摘要翻译：本发明提供了一种用于荧光灯的电子镇流器，包括用于将交流输入电压转换成直流输出电压的整流器，以及包括组合功率因数校正（PFC）级和逆变器的电路，其中PFC级和变频器共用开关。还提供了一种用于电子镇流器的控制器，包括控制镇流器开关的占空比的占空比控制器，以及根据非线性功能来调节占空比的装置，使得在整个灯上保持电弧。控制器和镇流器允许荧光灯调光，同时保持高功率因数。

6. 发明授权

US08779674B2 Electronic ballast with high power factor 失效
标题翻译：电子镇流器具有高功率因数
公开(公告)号：US08779674B2
公开(公告)日：2014-07-15
申请号：US13391491
申请日：2010-08-20
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B37/00 , H05B39/00 , H05B41/14
CPC分类号： H05B41/2824 , Y02B20/186
摘要： This invention provides an integrated power supply for a controller of an electronic ballast for a fluorescent lamp. The integrated power supply couples output power from the electronic ballast and uses the coupled power to provide power to the controller. In one embodiment, the electronic ballast may include a rectifier for converting an alternating current input voltage into a direct current output voltage, and a circuit including a combined power factor correction (PFC) stage and an inverter, wherein the PFC stage and the inverter share a switch. Also provided is a controller for an electronic ballast. The controller may include a voltage mode or current mode duty ratio controller that controls a duty ratio of a switch of the ballast. The controller and the ballast allow dimming of the fluorescent lamp while maintaining a high power factor.
摘要翻译：本发明提供一种用于荧光灯的电子镇流器的控制器的集成电源。集成电源耦合来自电子镇流器的输出功率，并使用耦合功率向控制器供电。在一个实施例中，电子镇流器可以包括用于将交流输入电压转换成直流输出电压的整流器，以及包括组合功率因数校正（PFC）级和反相器的电路，其中PFC级和逆变器共享一个开关还提供了一种用于电子镇流器的控制器。控制器可以包括控制镇流器开关的占空比的电压模式或电流模式占空比控制器。控制器和镇流器允许荧光灯调光，同时保持高功率因数。

7. 发明申请

US20120146526A1 Electronic Ballast with High Power Factor 失效
标题翻译：高功率因数电子镇流器
公开(公告)号：US20120146526A1
公开(公告)日：2012-06-14
申请号：US13391491
申请日：2010-08-20
申请人： John Lam , Praveen Jain
发明人： John Lam , Praveen Jain
IPC分类号： H05B37/02
CPC分类号： H05B41/2824 , Y02B20/186
摘要： This invention provides an integrated power supply for a controller of an electronic ballast for a fluorescent lamp. The integrated power supply couples output power from the electronic ballast and uses the coupled power to provide power to the controller. In one embodiment, the electronic ballast may include a rectifier for converting an alternating current input voltage into a direct current output voltage, and a circuit including a combined power factor correction (PFC) stage and an inverter, wherein the PFC stage and the inverter share a switch. Also provided is a controller for an electronic ballast. The controller may include a voltage mode or current mode duty ratio controller that controls a duty ratio of a switch of the ballast. The controller and the ballast allow dimming of the fluorescent lamp while maintaining a high power factor.
摘要翻译：本发明提供一种用于荧光灯的电子镇流器的控制器的集成电源。集成电源耦合来自电子镇流器的输出功率，并使用耦合功率向控制器供电。在一个实施例中，电子镇流器可以包括用于将交流输入电压转换成直流输出电压的整流器，以及包括组合功率因数校正（PFC）级和反相器的电路，其中PFC级和逆变器共享一个开关还提供了一种用于电子镇流器的控制器。控制器可以包括控制镇流器开关的占空比的电压模式或电流模式占空比控制器。控制器和镇流器允许荧光灯调光，同时保持高功率因数。

8. 发明授权

US07343569B1 Apparatus and method for reset distribution 有权
标题翻译：复位分配的装置和方法
公开(公告)号：US07343569B1
公开(公告)日：2008-03-11
申请号：US11351425
申请日：2006-02-10
申请人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
发明人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/66
摘要： A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.
摘要翻译：在支持多通道输入/输出协议的知识产权（IP）块中提供了容错，无毛刺的复位分配装置和方法。在复位模式期间，使用同步器创建更可预测的时序，流水线传播延迟，并允许在将复位信号路由到IP模块中的所有通道和通道内的RC时钟周期的RC引起的偏差。两个控制信号可从可编程逻辑资源核心电路获得，用于控制复位信号输入到IP模块。由于控制信号被设计为无毛刺，因此复位信号也无毛刺，从而防止IP块无意中转换或复位。

9. 发明授权

US06954424B2 Credit-based pacing scheme for heterogeneous speed frame forwarding 有权
标题翻译：用于异构速度帧转发的基于信用的起搏方案
公开(公告)号：US06954424B2
公开(公告)日：2005-10-11
申请号：US09794184
申请日：2001-02-26
申请人： Craig I. Barrack , Brian Yang , John Lam , Rong-Feng Chang
发明人： Craig I. Barrack , Brian Yang , John Lam , Rong-Feng Chang
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L47/10 , H04L47/39 , H04L49/25 , H04L49/30 , H04L49/505
摘要： A credit-based pacing scheme for heterogeneous speed frame forwarding. A control logic controls the transmission of data between a source device and a destination device in accordance with a handshaking protocol. Pacing logic paces the transmission of the data from the source device to the destination device to prevent congestion in the switching fabric. A credit scheme is used to arbitrate among multiple pacing modules per device, each forwarding data at a different rate.
摘要翻译：用于异构速度帧转发的基于信用的起搏方案。控制逻辑根据握手协议来控制源设备和目的地设备之间的数据传输。起搏逻辑将数据从源设备传输到目标设备，以防止交换结构中的拥塞。信用方案用于在每个设备的多个起搏模块之间进行仲裁，每个转发数据以不同的速率转发。

10. 发明授权

US6154059A High performance output buffer 有权
标题翻译：高性能输出缓冲器
公开(公告)号：US6154059A
公开(公告)日：2000-11-28
申请号：US199705
申请日：1998-11-24
申请人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
发明人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.
摘要翻译：输出缓冲器具有连接在输入节点和输出节点之间的内部电路。内部电路包括连接到内部电路的第一组晶体管的静音电压源和连接到内部电路的第二组晶体管的噪声电压源。嘈杂的电源电压处于高于静态电源的电压电平。第一组晶体管和第二组晶体管提供噪声电压源和安静电源之间的隔离。第一组晶体管和第二组晶体管还通过使用至少一个晶体管提供完整的数字高和低内部信号电平，该晶体管可操作地补充第一组晶体管的晶体管的完全截止和导通，第二组晶体管的第二组一组晶体管。输出缓冲器还具有接地反弹电路，压摆率控制电路，转换加速器电路，个人计算机接口（PCI）兼容性电路和PCI控制电路。

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