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1. 发明授权

US09736086B1 Multi-function, multi-protocol FIFO for high-speed communication 有权
公开(公告)号：US09736086B1
公开(公告)日：2017-08-15
申请号：US13098361
申请日：2011-04-29
申请人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
发明人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
IPC分类号： H04L12/861
CPC分类号： H04L49/90 , H04L47/6245
摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

2. 发明授权

US07984209B1 Data interface methods and circuitry with reduced latency 有权
标题翻译：具有降低延迟的数据接口方法和电路
公开(公告)号：US07984209B1
公开(公告)日：2011-07-19
申请号：US11638150
申请日：2006-12-12
申请人： Vinson Chan , Michael Menghui Zheng , Chong H. Lee
发明人： Vinson Chan , Michael Menghui Zheng , Chong H. Lee
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.
摘要翻译：用于在可能具有一些不同速度的两种不同时钟制式之间对数据进行接口的接口电路包括确定哪个时钟方案更快的能力。根据哪个时钟状态被发现更快，基线（数据写入和接口电路中的FIFO存储器的数据读取地址之间的标称差）被移位（即，朝向FIFO的满或空状态，如适用的那样）为什么时钟制度被发现是更快）。还可以对用于诸如字符插入/删除和溢出/下溢指示的目的的阈值进行调整。该技术可以允许使用较小的FIFO并减少接口电路的延迟。

3. 发明授权

US07046174B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US07046174B1
公开(公告)日：2006-05-16
申请号：US11147757
申请日：2005-06-07
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0331
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

4. 发明授权

US06724328B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06724328B1
公开(公告)日：2004-04-20
申请号：US10454626
申请日：2003-06-03
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M900
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

5. 发明授权

US06323680B1 Programmable logic device configured to accommodate multiplication 有权
标题翻译：配置为适应乘法的可编程逻辑器件
公开(公告)号：US06323680B1
公开(公告)日：2001-11-27
申请号：US09517350
申请日：2000-03-02
申请人： Bruce B. Pedersen , Sergey Shumarayev , Wei-Jen Huang , Vinson Chan , Stephen Brown , Tony Ngai , James Park
发明人： Bruce B. Pedersen , Sergey Shumarayev , Wei-Jen Huang , Vinson Chan , Stephen Brown , Tony Ngai , James Park
IPC分类号： G06F738
CPC分类号： H03K19/17736 , G06F7/5443 , H03K19/1737 , H03K19/17728 , H03K19/17732
摘要： A programmable logic device is configured to accommodate multiplication by the provision in each logic region of specialized components to form and sum partial products. The specialized components are separate from the ordinary logic of the logic region, and their presence imposes little penalty on the performance of ordinary logic functions, while enhancing the speed at which multiplication is performed by minimizing the number of logic regions used for a particular multiplication operation, and also minimizing the use of the interconnection resources of the device to convey signals among those regions.
摘要翻译：可编程逻辑器件被配置为通过专用部件的每个逻辑区域中的提供来适应乘法，以形成和求和部分乘积。专门的部件与逻辑区域的普通逻辑分开，并且它们的存在对普通逻辑功能的性能施加了很小的损失，同时通过最小化用于特定乘法运算的逻辑区域的数量来提高执行乘法的速度并且还最小化设备的互连资源在这些区域之间传送信号的使用。

6. 发明授权

US07095340B2 Run-length violation detection circuitry and methods for using the same 有权
标题翻译：运行长度违例检测电路及其使用方法
公开(公告)号：US07095340B2
公开(公告)日：2006-08-22
申请号：US11087217
申请日：2005-03-22
申请人： Vinson Chan , Chong Lee , Huy Ngo
发明人： Vinson Chan , Chong Lee , Huy Ngo
IPC分类号： H03M7/00
CPC分类号： H03M5/145
摘要： Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).
摘要翻译：提供了用于检测数据流中类似的数据位的过量运行的电路。数据流通常作为在串行时钟域中工作的串行数据来接收。与较快的串行时钟域相反，运行长度检测电路在较慢的并行时钟域中运行时检查运行长度违例的接收数据。在并行域中操作游程长度检测电路的优点是与在串行域中运行的游程长度检测器相比，可以在接收的数据中搜索更长的游程长度违例。电路提供的另一个优点是可以异步地将运行长度违规信号提供给利用电路。这使得尽管时钟域（即，检测电路的时钟域和利用电路的时钟域）有差异，但利用率电路可以快速地捕捉信号。

7. 发明申请

US20050162289A1 Run-length violation detection circuitry and methods for using the same 有权
标题翻译：运行长度违例检测电路及其使用方法
公开(公告)号：US20050162289A1
公开(公告)日：2005-07-28
申请号：US11087217
申请日：2005-03-22
申请人： Vinson Chan , Chong Lee , Huy Ngo
发明人： Vinson Chan , Chong Lee , Huy Ngo
IPC分类号： H03M5/14 , H03M7/00 , H03M7/46
CPC分类号： H03M5/145
摘要： Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. The circuitry of this of this invention checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage of the invention is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).
摘要翻译：提供了用于检测数据流中类似的数据位的过量运行的电路。数据流通常作为在串行时钟域中工作的串行数据来接收。与较快的串行时钟域相反，本发明的电路在较慢的并行时钟域中操作时检查所接收的数据的长度违反。在并行域中操作游程长度检测电路的优点是与在串行域中运行的游程长度检测器相比，可以在接收的数据中搜索更长的游程长度违例。本发明的另一个优点是可以异步地将游程长度违规信号提供给利用电路。这使得尽管时钟域（即，检测电路的时钟域和利用电路的时钟域）有差异，但利用率电路可以快速地捕捉信号。

8. 发明授权

US06888480B1 Run-length violation detection circuitry and methods for using the same 有权
标题翻译：运行长度违例检测电路及其使用方法
公开(公告)号：US06888480B1
公开(公告)日：2005-05-03
申请号：US10652907
申请日：2003-08-28
申请人： Vinson Chan , Chong Lee , Huy Ngo
发明人： Vinson Chan , Chong Lee , Huy Ngo
IPC分类号： H03M5/14 , H03M7/00
CPC分类号： H03M5/145
摘要： Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).
摘要翻译：提供了用于检测数据流中类似的数据位的过量运行的电路。数据流通常作为在串行时钟域中工作的串行数据来接收。与较快的串行时钟域相反，运行长度检测电路在较慢的并行时钟域中运行时检查运行长度违例的接收数据。在并行域中操作游程长度检测电路的优点是与在串行域中运行的游程长度检测器相比，可以在接收的数据中搜索更长的游程长度违例。电路提供的另一个优点是可以异步地将运行长度违规信号提供给利用电路。这使得尽管时钟域（即，检测电路的时钟域和利用电路的时钟域）有差异，但利用率电路可以快速地捕捉信号。

9. 发明授权

US06281704B1 High-performance interconnect 有权
公开(公告)号：US06281704B1
公开(公告)日：2001-08-28
申请号：US09810116
申请日：2001-03-15
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

10. 发明授权

US09170952B1 Configurable multi-standard device interface 有权
标题翻译：可配置的多标准设备接口
公开(公告)号：US09170952B1
公开(公告)日：2015-10-27
申请号：US13338707
申请日：2011-12-28
申请人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
发明人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
IPC分类号： G06F13/00 , G06F12/02 , G06F12/08 , G06F13/12 , G06F13/14 , G06F11/00 , H01L25/00 , H04J3/06
CPC分类号： G06F12/0862 , G06F13/00 , H03K19/17744
摘要： A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.
摘要翻译：可配置接口包括发射器模块和接收器模块，每个发送器模块和接收器模块被配置为根据至少三个不同的接口标准进行操作。所述可配置接口还包括接口模块，所述接口模块被配置为确定耦合到所述可配置接口的PMA的物理介质连接（PMA）标准，并基于所述PMA标准激活所述可配置接口的至少一个组件。在这种安排中，设备接口支持CAUI-4标准。

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