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1. 发明授权

US07940877B1 Signal edge detection circuitry and methods 有权
标题翻译：信号边缘检测电路和方法
公开(公告)号：US07940877B1
公开(公告)日：2011-05-10
申请号：US10819556
申请日：2004-04-06
申请人： John Oh , Samson Tam , Curt Wortman , Jean Luc Berube
发明人： John Oh , Samson Tam , Curt Wortman , Jean Luc Berube
IPC分类号： H04L25/40 , H04L7/00
CPC分类号： H04L7/0337 , H03K5/1534 , H03K5/26 , H03M9/00 , H04L7/0037 , H04L7/046
摘要： Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.
摘要翻译：双数据速率（“DDR”）电路等被修改或增强以包括边缘检测能力。在边缘检测模式期间，电路被提供有包括连续的等位位对的串行训练数据。多个不同阶段的候选时钟信号按照逐渐增加的相位顺序逐个使用以对DDR电路进行时钟。训练数据中相邻位应该是等值的由DDR电路捕获并进行比较。导致这样比较的位不相等的任何候选时钟信号被标记为具有接近数据边缘的相位。因此，数据边缘的大致相位由候选时钟信号（或信号）的相位（或相位）指示，使得如上所述比较的比特不相等。

2. 发明授权

US08416903B1 Signal edge detection circuitry and methods 有权
标题翻译：信号边缘检测电路和方法
公开(公告)号：US08416903B1
公开(公告)日：2013-04-09
申请号：US13097252
申请日：2011-04-29
申请人： John Oh , Samson Tam , Curt Wortman , Jean Luc Berube
发明人： John Oh , Samson Tam , Curt Wortman , Jean Luc Berube
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03K5/1534 , H03K5/26 , H03M9/00 , H04L7/0037 , H04L7/046
摘要： Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.
摘要翻译：双数据速率（DDR）电路等被修改或增强以包括边缘检测能力。在边缘检测模式期间，电路被提供有包括连续的等位位对的串行训练数据。多个不同阶段的候选时钟信号按照逐渐增加的相位顺序逐个使用以对DDR电路进行时钟。训练数据中相邻位应该是等值的由DDR电路捕获并进行比较。导致这样比较的位不相等的任何候选时钟信号被标记为具有接近数据边缘的相位。因此，数据边缘的大致相位由候选时钟信号（或信号）的相位（或相位）指示，使得如上所述比较的比特不相等。

3. 发明授权

US07295641B1 Phase alignment circuitry and methods 有权
标题翻译：相位对准电路和方法
公开(公告)号：US07295641B1
公开(公告)日：2007-11-13
申请号：US10722665
申请日：2003-11-26
申请人： Curt Wortman , Jean Luc Berube
发明人： Curt Wortman , Jean Luc Berube
IPC分类号： H04L25/00 , H04L25/40
CPC分类号： H04L7/0337 , H04L7/0037 , H04L7/046
摘要： The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling clock signal (derived from the reference clock signal). Information about which amounts of progressively greater phase shift in the sampling clock signal cause loss of alignment between a training pattern and training data in the data signal can be used for such purposes as identifying the amount of phase of shift of the reference clock signal that will be best for use in sampling the data signal during normal (post-training) operation.
摘要翻译：相对于参考时钟信号的数据信号的相位在采样时钟信号的试验版本（从参考时钟信号导出）之间仅使用相对粗略的相移增量来相对精确地近似。关于采样时钟信号中的逐渐增大的相移量导致训练模式与数据信号中的训练数据之间的对准损失的信息可以用于识别参考时钟信号的移位相位的量在正常（后培训）操作期间，最好用于对数据信号进行采样。

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