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1. 发明授权

US08614925B2 Semiconductor memory device having a redundancy area 有权
标题翻译：具有冗余区域的半导体存储器件
公开(公告)号：US08614925B2
公开(公告)日：2013-12-24
申请号：US12814776
申请日：2010-06-14
申请人： Joonmin Park , Beakhyung Cho , Kwangjin Lee , Hye-Jin Kim
发明人： Joonmin Park , Beakhyung Cho , Kwangjin Lee , Hye-Jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C29/808
摘要： Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.
摘要翻译：提供了一种半导体存储器件。半导体存储器包括主区域和冗余区域。主区域包括共享写入位线和读取位线的多个存储器块。冗余区域包括共享冗余写位线和冗余读位线的多个冗余存储块。提供冗余区域以替换具有缺陷的主区域中的部件。

2. 发明申请

US20100329053A1 SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY AREA 有权
标题翻译：具有冗余区域的半导体存储器件
公开(公告)号：US20100329053A1
公开(公告)日：2010-12-30
申请号：US12814776
申请日：2010-06-14
申请人： Joonmin Park , Beakhyung Cho , Kwangjin Lee , Hye-Jin Kim
发明人： Joonmin Park , Beakhyung Cho , Kwangjin Lee , Hye-Jin Kim
IPC分类号： G11C29/04 , G11C8/00
CPC分类号： G11C29/785 , G11C29/808
摘要： Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.
摘要翻译：提供了一种半导体存储器件。半导体存储器包括主区域和冗余区域。主区域包括共享写位线和读位线的多个存储块。冗余区域包括共享冗余写位线和冗余读位线的多个冗余存储块。提供冗余区域以替换具有缺陷的主区域中的部件。

3. 发明申请

US20100091553A1 SEMICONDUCTOR DEVICE HAVING RESISTANCE BASED MEMORY ARRAY AND METHOD OF OPERATION ASSOCIATED THEREWITH 有权
标题翻译：具有基于电阻的存储器阵列的半导体器件和与之相关的操作方法
公开(公告)号：US20100091553A1
公开(公告)日：2010-04-15
申请号：US12646345
申请日：2009-12-23
申请人： Yong-Jun Lee , Kwangjin Lee , Taek-Sung Kim , Kwangho Kim , Wooyeong Cho , Hyunho Choi , Hye-Jin Kim , Qi Wang
发明人： Yong-Jun Lee , Kwangjin Lee , Taek-Sung Kim , Kwangho Kim , Wooyeong Cho , Hyunho Choi , Hye-Jin Kim , Qi Wang
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0097 , G11C2013/0078 , G11C2213/72
摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。控制电路被配置为存储至少一个擦除指示符。擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

4. 发明授权

US08254158B2 Semiconductor device having resistance based memory array and method of operation associated therewith 有权
标题翻译：具有基于电阻的存储器阵列的半导体器件和与其相关联的操作方法
公开(公告)号：US08254158B2
公开(公告)日：2012-08-28
申请号：US12646345
申请日：2009-12-23
申请人： Yong-Jun Lee , Kwangjin Lee , Taek-Sung Kim , Kwangho Kim , Wooyeong Cho , Hyunho Choi , Hye-Jin Kim , Qi Wang
发明人： Yong-Jun Lee , Kwangjin Lee , Taek-Sung Kim , Kwangho Kim , Wooyeong Cho , Hyunho Choi , Hye-Jin Kim , Qi Wang
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0097 , G11C2013/0078 , G11C2213/72
摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。控制电路被配置为存储至少一个擦除指示符。擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

5. 发明授权

US08873776B2 Piezoelectric speaker 有权
标题翻译：压电扬声器
公开(公告)号：US08873776B2
公开(公告)日：2014-10-28
申请号：US13289225
申请日：2011-11-04
申请人： Hye-Jin Kim , Woo Seok Yang , Jong Dae Kim
发明人： Hye-Jin Kim , Woo Seok Yang , Jong Dae Kim
IPC分类号： H04R25/00
CPC分类号： H04R17/005 , H04R2201/003 , H04R2307/025 , H04R2499/15
摘要： Disclosed is a piezoelectric speaker including: a piezoelectric layer that converts electrical signals into oscillation and outputs sound; an electrode that is formed on a top or a bottom of the piezoelectric layer to apply the electrical signals to the piezoelectric layer; an acoustic diaphragm that is made of a hetero material including a first acoustic diaphragm and a second acoustic diaphragm and is attached to the bottom of the piezoelectric layer on which the electrode is formed; and a frame attached in a form enclosing a side of the acoustic diaphragm.
摘要翻译：公开了一种压电扬声器，包括：将电信号转换为振荡并输出声音的压电层; 形成在压电层的顶部或底部上以将电信号施加到压电层的电极; 由包括第一声膜和第二声膜的异质材料制成并附着在其上形成有电极的压电层的底部的声膜; 以及以包围隔膜的一侧的形式附接的框架。

6. 发明申请

US20130161788A1 Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer 有权
标题翻译：半导体封装包括堆叠半导体芯片和再分配层
公开(公告)号：US20130161788A1
公开(公告)日：2013-06-27
申请号：US13725132
申请日：2012-12-21
申请人： Sung-Hoon Chun , Hye-Jin Kim , Sang-Ho An , Kyung-Man Kim , Seok-Chan Lee
发明人： Sung-Hoon Chun , Hye-Jin Kim , Sang-Ho An , Kyung-Man Kim , Seok-Chan Lee
IPC分类号： H01L23/50
CPC分类号： H01L23/50 , H01L23/5223 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L28/40 , H01L2224/02166 , H01L2224/02375 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/06102 , H01L2224/06135 , H01L2224/131 , H01L2224/16135 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/48195 , H01L2224/48227 , H01L2224/48463 , H01L2224/48465 , H01L2224/49109 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.
摘要翻译：提供包括堆叠半导体芯片的半导体封装。半导体封装可以包括顺序堆叠在板上的第一半导体芯片和第二半导体芯片。半导体封装还可以包括存储器芯片上的布线层，并且布线层可以包括再分配图案和再分布垫。每个存储器芯片可以包括数据焊盘。第一半导体芯片的数据焊盘可以经由第二半导体芯片电连接到板，一些再分布图案和一些再分布焊盘。

7. 发明授权

US08426956B2 Semiconductor package structure having plural packages in a stacked arrangement 有权
标题翻译：具有堆叠布置的多个封装的半导体封装结构
公开(公告)号：US08426956B2
公开(公告)日：2013-04-23
申请号：US12855322
申请日：2010-08-12
申请人： In-Sang Song , Hye-Jin Kim , Kyung-Man Kim
发明人： In-Sang Song , Hye-Jin Kim , Kyung-Man Kim
IPC分类号： H01L23/488
CPC分类号： H01L25/105 , H01L21/568 , H01L23/481 , H01L23/49833 , H01L25/0657 , H01L2224/02377 , H01L2224/05548 , H01L2224/05568 , H01L2224/13024 , H01L2224/32145 , H01L2224/32225 , H01L2224/9205 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： The semiconductor package structure includes first and second packages. The first package has at least one first semiconductor chip disposed on a first printed circuit board, and at least one first pad disposed on the at least one first semiconductor chip. The second package has at least one second pad disposed on the first package, and at least one second semiconductor chip disposed on the at least one second pad. The at least one first semiconductor chip is electrically connected to the first printed circuit board. The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one second pad faces the at least one first pad.
摘要翻译：半导体封装结构包括第一和第二封装。第一封装具有设置在第一印刷电路板上的至少一个第一半导体芯片和设置在至少一个第一半导体芯片上的至少一个第一焊盘。所述第二封装具有设置在所述第一封装上的至少一个第二焊盘以及设置在所述至少一个第二焊盘上的至少一个第二半导体芯片。所述至少一个第一半导体芯片电连接到所述第一印刷电路板。所述至少一个第二焊盘电连接到所述至少一个第二半导体芯片。所述至少一个第二垫面对所述至少一个第一垫。

8. 发明授权

US08399992B2 Package-on-package type semiconductor package 有权
标题翻译：封装封装型半导体封装
公开(公告)号：US08399992B2
公开(公告)日：2013-03-19
申请号：US12872448
申请日：2010-08-31
申请人： Sung-Kyu Park , Tae-Sung Park , Kyung-Man Kim , Hye-Jin Kim
发明人： Sung-Kyu Park , Tae-Sung Park , Kyung-Man Kim , Hye-Jin Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.
摘要翻译：提供半导体封装及其制造方法。半导体封装包括下封装，其包括下基板，安装在下基板上的下半导体芯片，并且包括再分布，以及模制下半导体芯片的模制层，上封装，包括上基板和上半导体芯片，上部衬底，其中上部封装堆叠在下部封装上。所述半导体封装还包括电连接器，所述电互连器从所述上衬底延伸到所述模制层中并且连接到所述重新分配以将所述上部和下部封装彼此电连接;以及虚设互连器，其从所述上衬底延伸到所述模制层中以物理耦合上下包装彼此。

9. 发明授权

US08085575B2 Nonvolatile memory device and method of driving the same 有权
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：US08085575B2
公开(公告)日：2011-12-27
申请号：US12585728
申请日：2009-09-23
申请人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C7/02 , G11C7/12 , G11C7/18 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.
摘要翻译：提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

10. 发明授权

US07750453B2 Semiconductor device package with groove 有权
标题翻译：半导体器件封装带槽
公开(公告)号：US07750453B2
公开(公告)日：2010-07-06
申请号：US11855958
申请日：2007-09-14
申请人： Hye-Jin Kim , Kyung-Man Kim
发明人： Hye-Jin Kim , Kyung-Man Kim
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48471 , H01L2224/49175 , H01L2224/73265 , H01L2225/06565 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554
摘要： A semiconductor device package includes a semiconductor chip having bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion of the edge of the semiconductor chip; an adhesive material provided for adhering the bottom of the semiconductor chip to the insulation pattern to mount the semiconductor chip on the PCB; bonding wires provided for electrically connecting the bonding electrodes to the corresponding bonding pads; and a molding material provided for sealing the PCB, the semiconductor chip, the adhesive material, and the bonding wires.
摘要翻译：半导体器件封装包括具有接合焊盘的半导体芯片; 包括具有凹槽的绝缘图案和与所述接合焊盘对应的接合电极的印刷电路板（PCB），所述凹槽对应于所述半导体芯片的边缘并形成为部分地暴露所述半导体芯片的边缘的下部; 提供用于将半导体芯片的底部粘附到绝缘图案以将半导体芯片安装在PCB上的粘合材料; 用于将接合电极电连接到相应的接合焊盘的接合线; 以及用于密封PCB，半导体芯片，粘合材料和接合线的成型材料。

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