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1. 发明授权

US08310856B2 Ferroelectric memories based on arrays of autonomous memory bits 有权
标题翻译：基于自主存储器位阵列的铁电存储器
公开(公告)号：US08310856B2
公开(公告)日：2012-11-13
申请号：US12797539
申请日：2010-06-09
申请人： Joseph Tate Evans, Jr.
发明人： Joseph Tate Evans, Jr.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory having a plurality of ferroelectric memory cells connected between first and second bit lines is disclosed. A read circuit is also connected between the first and second bit lines. A word select circuit selects one of the ferroelectric memory cells and generates a potential on the first hit line indicative of a value stored in the selected one of the plurality of ferroelectric memory cells. Each ferroelectric memory cell includes a ferroelectric capacitor and a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal. The ferroelectric capacitor is connected between the control terminal and the first switch terminal. First and second gates connect the ferroelectric memory cell to the bit lines in response to the word select circuit selecting that ferroelectric memory cell.
摘要翻译：公开了一种具有连接在第一和第二位线之间的多个铁电存储单元的存储器。读取电路也连接在第一和第二位线之间。字选择电路选择铁电存储单元之一，并在第一命中行上生成表示存储在所选择的多个铁电存储单元中的值的电位。每个铁电存储单元包括铁电电容器和可变阻抗元件，其具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗。铁电电容器连接在控制端子和第一开关端子之间。响应于选择该铁电存储单元的字选择电路，第一和第二栅极将铁电存储单元连接到位线。

2. 发明授权

US5840620A Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures 失效
标题翻译：在密封结构中恢复加热后氧化铟半导体电阻的方法
公开(公告)号：US5840620A
公开(公告)日：1998-11-24
申请号：US577851
申请日：1995-12-22
申请人： Carleton H. Seager , Joseph Tate Evans, Jr.
发明人： Carleton H. Seager , Joseph Tate Evans, Jr.
IPC分类号： H01C17/26 , H01L31/18 , H01L21/477
CPC分类号： H01C17/265 , H01L31/1884 , Y02E10/50
摘要： A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.
摘要翻译：当氧化铟电阻层在半导体器件制造期间经受高温退火步骤时，抵消遇到的电阻增加的方法。该方法利用恢复退火步骤，其在高温退火步骤使电阻率增加之后将氧化铟层返回其原始电阻率。回收退火包括将电阻层加热至100℃至300℃的温度一段取决于退火温度的时间。即使氧化铟层被密封在电介质层下，也可观察到回收。

3. 发明授权

US08565000B2 Variable impedance circuit controlled by a ferroelectric capacitor 有权
标题翻译：可变阻抗电路由铁电电容控制
公开(公告)号：US08565000B2
公开(公告)日：2013-10-22
申请号：US13223815
申请日：2011-09-01
申请人： Joseph Tate Evans, Jr.
发明人： Joseph Tate Evans, Jr.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.
摘要翻译：公开了一种包括铁电电容器，可变阻抗元件和导电负载的存储单元。特征在于第一和第二极化状态的铁电电容器连接在控制端子和第一开关端子之间。可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗。导电负载连接在第一电源端子和第一开关端子之间。第二开关端子连接到第二电源端子。当在第一和第二电源端子之间施加电位差时，第一开关端子上的电位以由铁电体电容器的极化状态确定的方式变化。

4. 发明授权

US07990749B2 Variable impedance circuit controlled by a ferroelectric capacitor 有权
标题翻译：可变阻抗电路由铁电电容控制
公开(公告)号：US07990749B2
公开(公告)日：2011-08-02
申请号：US12480645
申请日：2009-06-08
申请人： Joseph Tate Evans, Jr.
发明人： Joseph Tate Evans, Jr.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.
摘要翻译：公开了一种包括铁电电容器，可变阻抗元件和导电负载的存储单元。特征在于第一和第二极化状态的铁电电容器连接在控制端子和第一开关端子之间。可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗。导电负载连接在第一电源端子和第一开关端子之间。第二开关端子连接到第二电源端子。当在第一和第二电源端子之间施加电位差时，第一开关端子上的电位以由铁电体电容器的极化状态确定的方式变化。

5. 发明授权

US06459137B1 Method for constructing ferroelectric capacitors on integrated circuit substrates 失效
标题翻译：在集成电路基板上构造铁电电容器的方法
公开(公告)号：US06459137B1
公开(公告)日：2002-10-01
申请号：US08501945
申请日：1995-07-13
申请人： Jeff Allen Bullington , Carl Elijah Montross, Jr. , Joseph Tate Evans, Jr.
发明人： Jeff Allen Bullington , Carl Elijah Montross, Jr. , Joseph Tate Evans, Jr.
IPC分类号： H01L2900
CPC分类号： H01L28/60
摘要： A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO2 or Si3N4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond, the bottom electrode to the substrate surface.
摘要翻译：公开了一种铁电电容器及其制造方法。铁电电容器可以构造在诸如SiO 2或Si 3 N 4的硅衬底上。铁电体电容器包括底部电极，铁电体层和顶部电极。底部电极由铂层构成，其通过一层金属氧化物结合到硅衬底。金属氧化物不会扩散到铂中; 因此，可以将较薄的铂层用于电极。这降低了电容器的垂直高度以及与用于将底部电极结合到衬底表面的层的扩散相关的其它问题。

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