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1. 发明申请

US20120292598A1 EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS 有权
标题翻译：外延源/漏极触点自定义到沉积FET通道的栅极
公开(公告)号：US20120292598A1
公开(公告)日：2012-11-22
申请号：US13565342
申请日：2012-08-02
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/775
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

2. 发明授权

US08513099B2 Epitaxial source/drain contacts self-aligned to gates for deposited FET channels 有权
标题翻译：外延源极/漏极接触件自对准到用于沉积FET通道的栅极
公开(公告)号：US08513099B2
公开(公告)日：2013-08-20
申请号：US12817733
申请日：2010-06-17
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

3. 发明授权

US08754403B2 Epitaxial source/drain contacts self-aligned to gates for deposited FET channels 有权
标题翻译：外延源极/漏极接触件自对准到用于沉积FET通道的栅极
公开(公告)号：US08754403B2
公开(公告)日：2014-06-17
申请号：US13565342
申请日：2012-08-02
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/06
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

4. 发明申请

US20110309332A1 EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS 有权
标题翻译：外延源/漏极触点自定义到沉积FET通道的栅极
公开(公告)号：US20110309332A1
公开(公告)日：2011-12-22
申请号：US12817733
申请日：2010-06-17
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L29/78 , H01L21/84
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

5. 发明授权

US07893492B2 Nanowire mesh device and method of fabricating same 有权
标题翻译：纳米线网装置及其制造方法
公开(公告)号：US07893492B2
公开(公告)日：2011-02-22
申请号：US12371943
申请日：2009-02-17
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译：提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

6. 发明授权

US08703576B2 Gap-fill keyhole repair using printable dielectric material 失效
公开(公告)号：US08703576B2
公开(公告)日：2014-04-22
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/76
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.

7. 发明申请

US20130062709A1 Gap-Fill Keyhole Repair Using Printable Dielectric Material 失效
标题翻译：使用可印刷介质材料进行缺陷孔眼修复
公开(公告)号：US20130062709A1
公开(公告)日：2013-03-14
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.
摘要翻译：在半导体衬底上形成一次性栅极结构。平坦化电介质层沉积在一次性栅极结构上并且被平坦化以提供与一次性栅极结构的顶表面共面的顶表面。此时的平坦化电介质层包括狭缝间隔一次性栅极结构之间的间隙填充键孔。在平坦化介电层上沉积可印刷介电层以填充间隙填充键孔。在间隙填充键孔上的可印刷电介质层的区域被可印刷介电层的材料中交叉连接的辐射辐射照射。可打印介电层的非交联部分随后被选择性地移除到可印刷介电层的交联部分，该可印刷电介质层至少填充每个栅极填充孔眼的上部。去除一次性门结构以形成门腔。栅极腔填充有栅极电介质和栅电极。

8. 发明授权

US09024355B2 Embedded planar source/drain stressors for a finFET including a plurality of fins 有权
标题翻译：用于包括多个翅片的finFET的嵌入式平面源极/漏极应力源
公开(公告)号：US09024355B2
公开(公告)日：2015-05-05
申请号：US13483200
申请日：2012-05-30
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66484 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7831 , H01L29/7848 , H01L29/785
摘要： Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.
摘要翻译：翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。在形成平坦化介电层之后，去除一次性栅极结构。使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。在多个半导体鳍片上形成替换栅极结构。

9. 发明授权

US08981478B2 Recessed source and drain regions for FinFETs 有权
标题翻译：嵌入式FinFET的源极和漏极区域
公开(公告)号：US08981478B2
公开(公告)日：2015-03-17
申请号：US13611335
申请日：2012-09-12
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
摘要翻译：半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。

10. 发明申请

US20130320399A1 EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS 有权
标题翻译：嵌入式平面电源/漏极应力器，包括多个FINS
公开(公告)号：US20130320399A1
公开(公告)日：2013-12-05
申请号：US13483200
申请日：2012-05-30
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66484 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7831 , H01L29/7848 , H01L29/785
摘要： Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.
摘要翻译：翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。在形成平坦化介电层之后，去除一次性栅极结构。使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。在多个半导体鳍片上形成替换栅极结构。

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