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1. 发明申请

US20100044800A1 High-K dielectric metal gate device structure 有权
标题翻译：高K电介质金属栅极器件结构
公开(公告)号：US20100044800A1
公开(公告)日：2010-02-25
申请号：US12589421
申请日：2009-10-23
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.
摘要翻译：金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。

2. 发明授权

US07625791B2 High-k dielectric metal gate device structure and method for forming the same 有权
标题翻译：高k电介质金属栅极器件结构及其形成方法
公开(公告)号：US07625791B2
公开(公告)日：2009-12-01
申请号：US11926830
申请日：2007-10-29
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.
摘要翻译：金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

3. 发明授权

US07829949B2 High-K dielectric metal gate device structure 有权
公开(公告)号：US07829949B2
公开(公告)日：2010-11-09
申请号：US12589421
申请日：2009-10-23
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.

4. 发明申请

US20090108365A1 HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：高K介电金属栅组件结构及其形成方法
公开(公告)号：US20090108365A1
公开(公告)日：2009-04-30
申请号：US11926830
申请日：2007-10-29
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L27/092 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.
摘要翻译：金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

5. 发明授权

US08148249B2 Methods of fabricating high-k metal gate devices 有权
标题翻译：制造高k金属栅极器件的方法
公开(公告)号：US08148249B2
公开(公告)日：2012-04-03
申请号：US12405965
申请日：2009-03-17
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu-Chao Lin
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu-Chao Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/823828 , H01L21/3221 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
摘要翻译：公开了制造具有高k /金属栅极特征的半导体器件的方法。在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

6. 发明申请

US20100038721A1 METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS 有权
标题翻译：在高K /金属浇口工艺中形成单一金属的方法，其具有N个工作功能和P功能
公开(公告)号：US20100038721A1
公开(公告)日：2010-02-18
申请号：US12492889
申请日：2009-06-26
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Donald Y. Chao , Yi-Shien Mor , Kuo-Tai Huang
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Donald Y. Chao , Yi-Shien Mor , Kuo-Tai Huang
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/28194 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在半导体衬底上形成栅极电介质，在栅极电介质之上或之下形成覆盖层，在覆盖层上形成金属层，金属层具有第一功函数，处理金属层的一部分，使得所述金属层的所述部分的功函数从所述第一功函数变为第二功函数，并且从具有所述第一功函数的所述金属层的未处理部分形成第一金属栅极，并且从所述处理的所述金属栅极形成第二金属栅极具有第二功函数的金属层的部分。

7. 发明授权

US08524588B2 Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process 有权
标题翻译：在高k /金属栅极工艺中形成执行N功函数和P功函数的单一金属的方法
公开(公告)号：US08524588B2
公开(公告)日：2013-09-03
申请号：US12492889
申请日：2009-06-26
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Donald Y. Chao , Yi-Shien Mor , Kuo-Tai Huang
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Donald Y. Chao , Yi-Shien Mor , Kuo-Tai Huang
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/28194 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上或之下形成覆盖层，在覆盖层上形成金属层，金属层具有第一功函数，处理金属层的一部分，使得所述金属层的所述部分的功函数从所述第一功函数变化为第二功函数，并且从具有所述第一功函数的所述金属层的未处理部分形成第一金属栅极，并且从所述处理的所述第二金属栅极形成第二金属栅极具有第二功函数的金属层的部分。

8. 发明申请

US20120164822A1 METHODS OF FABRICATING HIGH-K METAL GATE DEVICES 有权
标题翻译：制造高K金属栅极器件的方法
公开(公告)号：US20120164822A1
公开(公告)日：2012-06-28
申请号：US13408016
申请日：2012-02-29
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/823828 , H01L21/3221 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
摘要翻译：公开了制造具有高k /金属栅极特征的半导体器件的方法。在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

9. 发明申请

US20100041223A1 METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW 有权
标题翻译：在CMOS工艺流程中集成高K /金属栅的方法
公开(公告)号：US20100041223A1
公开(公告)日：2010-02-18
申请号：US12478509
申请日：2009-06-04
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/82385 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/0653 , H01L29/401 , H01L29/42372 , H01L29/4966 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成第一金属层，第一金属层具有第一在第二有源区中除去第一金属层的一部分，然后在第一有源区中的第一金属层上方和在第二有源区中的部分去除的第一金属层上方形成半导体层，形成第一在第一有源区中的栅极堆叠和第二有源区中的第二栅极堆叠，从第一栅极堆叠和第二栅极堆叠中去除半导体层，以及在第一栅极堆叠中的第一金属层上形成第二金属层并且在第二栅极堆叠中部分去除的第一金属层上，第二金属层具有第二功函数。

10. 发明授权

US08551837B2 Methods of fabricating high-K metal gate devices 有权
标题翻译：制造高K金属栅极器件的方法
公开(公告)号：US08551837B2
公开(公告)日：2013-10-08
申请号：US13408016
申请日：2012-02-29
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu Chao Lin
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu Chao Lin
IPC分类号： H01L21/8242
CPC分类号： H01L21/823828 , H01L21/3221 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
摘要翻译：公开了制造具有高k /金属栅极特征的半导体器件的方法。在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

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