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1. 发明授权

US07157350B2 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
公开(公告)号：US07157350B2
公开(公告)日：2007-01-02
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

2. 发明申请

US20050253194A1 SOI-like structure in a bulk semiconductor substrate and method of forming same 有权
标题翻译：体半导体衬底中的SOI类结构及其形成方法
公开(公告)号：US20050253194A1
公开(公告)日：2005-11-17
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/324 , H01L21/762 , H01L27/01 , H01L27/12
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

3. 发明授权

US6046475A Structure and method for manufacturing devices having inverse T-shaped well regions 失效
标题翻译：用于制造具有反T形阱区的器件的结构和方法
公开(公告)号：US6046475A
公开(公告)日：2000-04-04
申请号：US864988
申请日：1997-05-29
申请人： Kow-Ming Chang , Ji-yi Yang , Ming-Ray Mao
发明人： Kow-Ming Chang , Ji-yi Yang , Ming-Ray Mao
IPC分类号： H01L29/10 , H01L31/119
CPC分类号： H01L29/1079
摘要： A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower impurity concentration. The first doped region formed on the substrate by a high-energy ion-implantation process is kept at a predetermined distance from the surface of the substrate. The second doped region extends from the surface of the substrate toward the downside to connect to the first doped region, such that two third doped regions are formed. The second doped region is formed by an ion-implantation process through an opening of a mask. Furthermore, a gate is formed above the second doped region, and source and drain regions are formed on the substrate. Therefore, a device having an inverse T-shaped well region is completely fabricated.
摘要翻译：用于制造具有反T形阱区的器件的结构，其形成在衬底上，包括具有较高杂质浓度的第一掺杂区和第二掺杂区和具有较低杂质浓度的两个第三掺杂区。通过高能离子注入工艺在衬底上形成的第一掺杂区域保持在离衬底表面预定距离处。第二掺杂区域从衬底的表面向下延伸以连接到第一掺杂区域，使得形成两个第二掺杂区域。第二掺杂区域通过离子注入工艺通过掩模的开口形成。此外，在第二掺杂区域上方形成栅极，并且在衬底上形成源极和漏极区域。因此，具有逆T形阱区域的器件被完全制造。

4. 发明授权

US07327009B2 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US07327009B2
公开(公告)日：2008-02-05
申请号：US11620085
申请日：2007-01-05
申请人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L29/00
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

5. 发明申请

US20070105337A1 SELECTIVE NITRIDE LINER FORMATION FOR SHALLOW TRENCH ISOLATION 有权
标题翻译：选择性氮化物衬里形成用于浅层分离
公开(公告)号：US20070105337A1
公开(公告)日：2007-05-10
申请号：US11620085
申请日：2007-01-05
申请人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

6. 发明申请

US20070063282A1 SOI-like structures in a bulk semiconductor substrate 审中-公开
标题翻译：体半导体衬底中的SOI类结构
公开(公告)号：US20070063282A1
公开(公告)日：2007-03-22
申请号：US11599931
申请日：2006-11-15
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L27/12 , H01L29/00
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

7. 发明授权

US07829949B2 High-K dielectric metal gate device structure 有权
公开(公告)号：US07829949B2
公开(公告)日：2010-11-09
申请号：US12589421
申请日：2009-10-23
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.

8. 发明申请

US20090108365A1 HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：高K介电金属栅组件结构及其形成方法
公开(公告)号：US20090108365A1
公开(公告)日：2009-04-30
申请号：US11926830
申请日：2007-10-29
申请人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
发明人： Joshua Tseng , Kang-Cheng Lin , Ji-Yi Yang , Kuo-Tai Huang , Ryan Chia-Jen Chen
IPC分类号： H01L27/092 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.
摘要翻译：金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

9. 发明授权

US06284621B1 Semiconductor structure with a dielectric layer and its producing method 有权
标题翻译：具有介电层的半导体结构及其制造方法
公开(公告)号：US06284621B1
公开(公告)日：2001-09-04
申请号：US09239000
申请日：1999-01-27
申请人： Kow-Ming Chang , Ji-Yi Yang
发明人： Kow-Ming Chang , Ji-Yi Yang
IPC分类号： H01L21764
CPC分类号： H01L21/7682
摘要： A semiconductor structure with a dielectric layer and its producing method are disclosed. The semiconductor structure includes a semiconductor substrate having thereon a plurality of metal lines and there are a plurality of concave regions formed between the metal lines. The dielectric layer is formed on the semiconductor by a method which can prevent the dielectric material from flowing into the concave regions. The method includes the steps of (a) providing a semiconductor substrate having thereon a plurality of metal lines forming therebetween a plurality of concave regions; and (b) forming the dielectric layer on the metal lines. The concave regions are only filled with air so that the capacitance of the semiconductor is lowered.
摘要翻译：公开了具有介电层的半导体结构及其制造方法。半导体结构包括其上具有多个金属线的半导体衬底，并且在金属线之间形成有多个凹区。通过可以防止电介质材料流入凹入区域的方法在半导体上形成电介质层。该方法包括以下步骤：（a）提供其上形成有多个金属线之间的多个凹陷区域的半导体衬底; 和（b）在金属线上形成电介质层。凹区仅填充有空气，使得半导体的电容降低。

10. 发明授权

US07176138B2 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US07176138B2
公开(公告)日：2007-02-13
申请号：US10970090
申请日：2004-10-21
申请人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

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