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1. 发明授权

US09947684B2 Three-dimensional semiconductor device 有权
公开(公告)号：US09947684B2
公开(公告)日：2018-04-17
申请号：US15241781
申请日：2016-08-19
申请人： Joyoung Park , Yong-Hyun Kwon , Jeongsoo Kim , Seok-Won Lee , Jinwoo Park , Oik Kwon , Seungpil Chung
发明人： Joyoung Park , Yong-Hyun Kwon , Jeongsoo Kim , Seok-Won Lee , Jinwoo Park , Oik Kwon , Seungpil Chung
IPC分类号： H01L27/11 , H01L27/11582 , H01L27/11568
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L27/11575
摘要： A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

2. 发明申请

US20080113515A1 Methods of Forming Semiconductor Devices 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：US20080113515A1
公开(公告)日：2008-05-15
申请号：US11874267
申请日：2007-10-18
申请人： Hyun-Chul Kim , Sung-Il Cho , Eun-Young Kang , Yong-Hyun Kwon , Jae-Seung Hwang
发明人： Hyun-Chul Kim , Sung-Il Cho , Eun-Young Kang , Yong-Hyun Kwon , Jae-Seung Hwang
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/823437 , H01L27/105 , H01L29/66621
摘要： A method of forming a semiconductor device is provided. The method includes preparing a semiconductor substrate to include a cell region and a peripheral region and forming a first mask layer on the semiconductor substrate. First hard mask patterns that are configured to expose the first mask layer are formed on the first mask layer in the cell region. A second mask layer that is configured to conformably cover the first hard mask patterns is formed. A second hard mask pattern is formed between the first hard mask patterns, wherein the second hard mask pattern is configured to contact a lateral surface of the second mask layer. The second mask layer interposed between the first hard mask patterns and the second hard mask pattern is removed. A plurality of trenches are etched in the semiconductor substrate of the cell region using the first hard mask patterns and the second hard mask pattern as a mask.
摘要翻译：提供一种形成半导体器件的方法。该方法包括制备半导体衬底以包括单元区域和外围区域，并在半导体衬底上形成第一掩模层。配置为暴露第一掩模层的第一硬掩模图案形成在单元区域中的第一掩模层上。形成被构造为顺应地覆盖第一硬掩模图案的第二掩模层。在第一硬掩模图案之间形成第二硬掩模图案，其中第二硬掩模图案被配置为接触第二掩模层的侧表面。插入在第一硬掩模图案和第二硬掩模图案之间的第二掩模层被去除。使用第一硬掩模图案和第二硬掩模图案作为掩模，在单元区域的半导体衬底中蚀刻多个沟槽。

3. 发明授权

US08391057B2 Switch and method of forming the same 有权
标题翻译：开关及其形成方法
公开(公告)号：US08391057B2
公开(公告)日：2013-03-05
申请号：US12533581
申请日：2009-07-31
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
IPC分类号： G11C11/50 , H01L27/108
CPC分类号： H01L27/101 , H01L27/108 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/40 , H01L29/685
摘要： A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储器件包括存储单元，其包括存储节点，第一电极和第二电极，所述存储节点存储电荷，并且当所述第二电极通电时，所述第一电极移动以连接到所述存储节点。

4. 发明授权

US10224339B2 Semiconductor memory devices 有权
公开(公告)号：US10224339B2
公开(公告)日：2019-03-05
申请号：US15822586
申请日：2017-11-27
申请人： Gang Zhang , Hyuk Kim , Yong-Hyun Kwon , Sangwuk Park
发明人： Gang Zhang , Hyuk Kim , Yong-Hyun Kwon , Sangwuk Park
IPC分类号： H01L27/11573 , H01L27/11582 , H01L27/092 , H01L23/522 , H01L27/11575 , H01L27/12 , H01L27/1157 , H01L27/118
摘要： Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

5. 发明授权

US09831260B2 Semiconductor memory devices 有权
公开(公告)号：US09831260B2
公开(公告)日：2017-11-28
申请号：US15403829
申请日：2017-01-11
申请人： Gang Zhang , Hyuk Kim , Yong-Hyun Kwon , Sangwuk Park
发明人： Gang Zhang , Hyuk Kim , Yong-Hyun Kwon , Sangwuk Park
IPC分类号： H01L29/76 , G11C11/34 , H01L27/11573 , H01L27/12 , H01L23/522 , H01L27/11575 , H01L27/11582 , H01L27/092 , H01L27/118
CPC分类号： H01L27/11573 , H01L23/5226 , H01L27/0925 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L27/1207 , H01L2027/11861 , H01L2924/1438
摘要： Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

6. 发明授权

US08216944B2 Methods of forming patterns in semiconductor devices 有权
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US08216944B2
公开(公告)日：2012-07-10
申请号：US12715788
申请日：2010-03-02
申请人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
发明人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.
摘要翻译：提供了在半导体器件中形成图案的方法，包括在对象结构上形成彼此间隔开的第一图案。第一牺牲层在第一图案和对象结构上保形地形成。第二图案形成在第一牺牲层的侧壁上，第二图案具有比目标结构的上表面小的第一图案的高度。选择性地去除第一图案以形成露出对象结构的开口。第三图案形成在开口的侧壁上。

7. 发明申请

US20100221921A1 Methods of Forming Patterns in Semiconductor Devices 有权
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US20100221921A1
公开(公告)日：2010-09-02
申请号：US12715788
申请日：2010-03-02
申请人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
发明人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
IPC分类号： H01L21/3105
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.
摘要翻译：提供了在半导体器件中形成图案的方法，包括在对象结构上形成彼此间隔开的第一图案。第一牺牲层在第一图案和对象结构上保形地形成。第二图案形成在第一牺牲层的侧壁上，第二图案具有比目标结构的上表面小的第一图案的高度。选择性地去除第一图案以形成露出对象结构的开口。第三图案形成在开口的侧壁上。

8. 发明授权

US08871591B2 Methods of manufacturing a vertical type semiconductor device 有权
标题翻译：制造垂直型半导体器件的方法
公开(公告)号：US08871591B2
公开(公告)日：2014-10-28
申请号：US13600025
申请日：2012-08-30
申请人： Yong-Hyun Kwon , Dae-Hyun Jang , Seong-Soo Lee , Kyoung-Sub Shin
发明人： Yong-Hyun Kwon , Dae-Hyun Jang , Seong-Soo Lee , Kyoung-Sub Shin
IPC分类号： H01L21/336
CPC分类号： H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.
摘要翻译：根据本发明构思的示例性实施例，一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。形成第一反射限制层图案和第一光致抗蚀剂层图案，用于暴露第一初步接触孔，同时覆盖初始和初步接触孔的入口部分。在第一初步接触孔下方的层上进行第一蚀刻处理，以在比第一预接触孔的底部低的位置处露出电池图案。重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺，以形成具有不同深度的接触孔。

9. 发明申请

US20100135064A1 SWITCH AND METHOD OF FORMING THE SAME 有权
标题翻译：开关及其形成方法
公开(公告)号：US20100135064A1
公开(公告)日：2010-06-03
申请号：US12533581
申请日：2009-07-31
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： H01L27/101 , H01L27/108 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/40 , H01L29/685
摘要： A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储器件包括存储单元，其包括存储节点，第一电极和第二电极，所述存储节点存储电荷，并且当所述第二电极通电时，所述第一电极移动以连接到所述存储节点。

10. 发明申请

US20060151469A1 Cooking apparatus 审中-公开
标题翻译：烹饪器具
公开(公告)号：US20060151469A1
公开(公告)日：2006-07-13
申请号：US11283688
申请日：2005-11-22
申请人： Byoung-In Lee , Dong-won Kim , Seon-uk Na , Yong-Hyun Kwon , Seong-deog Jang , Chul Kim
发明人： Byoung-In Lee , Dong-won Kim , Seon-uk Na , Yong-Hyun Kwon , Seong-deog Jang , Chul Kim
IPC分类号： H05B3/68
CPC分类号： A47J37/0709
摘要： A cooking apparatus having a grill part to cook food thereon, and a grill housing coupled with the grill part, the cooking apparatus includes an electric heater provided in a middle region of the grill housing to be disposed at a lower side of the grill part, and a grill reflecting member reflecting heat generated from the electric heater to the grill part. The cooking apparatus enhances a cooking efficiency so that heat generated from an electric heater is efficiently transmitted to food.
摘要翻译：一种烹饪设备，具有用于在其上烹饪食物的格栅部分和与格栅部分连接的格栅外壳，所述烹饪设备包括设置在所述格栅外壳的中间区域中以设置在所述格栅部分的下侧的电加热器，以及将从电加热器产生的热反射到格栅部分的格栅反射部件。烹饪装置提高烹饪效率，使得从电加热器产生的热量有效地传递到食物。

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