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1. 发明授权

US08656321B1 Method of eliminating a lithography operation 有权
标题翻译：消除光刻操作的方法
公开(公告)号：US08656321B1
公开(公告)日：2014-02-18
申请号：US13183749
申请日：2011-07-15
申请人： Judy Huckabay , Milind Weling , Abdurrahman Sezginer
发明人： Judy Huckabay , Milind Weling , Abdurrahman Sezginer
IPC分类号： G06F17/50
CPC分类号： H01L21/0338 , H01L21/0334 , H01L21/0337 , H01L21/30621
摘要： Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.
摘要翻译：公开了使用双重图案化的半导体器件制造技术的方法。根据本发明的各种实施例，提供了使用自对准双重图案化的半导体器件制造方法。本发明的特定实施例允许使用两个光刻操作创建逻辑电路图案。本发明的一个实施例采用自对准双重图案化来定义具有两个相邻组之间的连接特征的两组或多组平行线特征。在这种实施例中，使用两个光刻掩模来形成平行线特征的集合以及连接特征，而不需要额外的掩模层来形成连接特征。在其他实施例中，除了连接特征之外的其他特征可以添加在相同的掩模层中。

2. 发明授权

US07856613B1 Method for self-aligned doubled patterning lithography 有权
标题翻译：自对准双重图案平版印刷的方法
公开(公告)号：US07856613B1
公开(公告)日：2010-12-21
申请号：US12264853
申请日：2008-11-04
申请人： Milind Weling , Judy Huckabay , Abdurrahman Sezginer
发明人： Milind Weling , Judy Huckabay , Abdurrahman Sezginer
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： H01L21/033 , G03F1/00
摘要： Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
摘要翻译：本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。

3. 发明授权

US08679981B1 Method for self-aligned doubled patterning lithography 有权
标题翻译：自对准双重图案平版印刷的方法
公开(公告)号：US08679981B1
公开(公告)日：2014-03-25
申请号：US12943808
申请日：2010-11-10
申请人： Milind Weling , Judy Huckabay , Abdurrahman Sezginer
发明人： Milind Weling , Judy Huckabay , Abdurrahman Sezginer
IPC分类号： H01L21/302
CPC分类号： H01L21/033 , G03F1/00
摘要： Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
摘要翻译：本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。

4. 发明授权

US08716135B1 Method of eliminating a lithography operation 有权
标题翻译：消除光刻操作的方法
公开(公告)号：US08716135B1
公开(公告)日：2014-05-06
申请号：US12264139
申请日：2008-11-03
申请人： Judy Huckabay , Milind Weling , Abdurrahman Sezginer
发明人： Judy Huckabay , Milind Weling , Abdurrahman Sezginer
IPC分类号： H01L21/308 , H01L21/033 , H01L21/306
CPC分类号： H01L21/0338 , H01L21/0334 , H01L21/0337 , H01L21/30621
摘要： Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.
摘要翻译：公开了使用双重图案化的半导体器件制造技术的方法。根据本发明的各种实施例，提供了使用自对准双重图案化的半导体器件制造方法。本发明的特定实施例允许使用两个光刻操作创建逻辑电路图案。本发明的一个实施例采用自对准双重图案化来定义两组或更多组具有组之间的连接特征的平行线特征。在这样的实施例中，使用两个光刻掩模来形成平行线特征的集合以及连接特征，而不需要额外的掩模层来形成连接。在其他实施例中，除了连接之外的其他特征可以添加在相同的掩模层中。

5. 发明授权

US08440569B2 Method of eliminating a lithography operation 有权
标题翻译：消除光刻操作的方法
公开(公告)号：US08440569B2
公开(公告)日：2013-05-14
申请号：US11952703
申请日：2007-12-07
申请人： Milind Weling , Abdurrahman Sezginer
发明人： Milind Weling , Abdurrahman Sezginer
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.
摘要翻译：公开了半导体器件制造方法。示例性方法包括在半导体衬底上沉积第一图案的过程，其中第一图案限定宽而窄的空间; 在衬底上的第一图案上沉积间隔物材料; 蚀刻间隔物材料，使得间隔物材料从基底和第一图案的水平表面移除，但保持邻近由第一图案限定的宽空间的垂直表面，并保持在由第一图案限定的狭窄空间内; 并从衬底去除第一图案。在一个实施例中，第一图案可以包括牺牲材料，其可以包括例如多晶硅材料。沉积可以包括物理气相沉积，化学气相沉积，电化学沉积，分子束外延，原子层沉积或其它沉积技术。根据另一个实施例，在相同掩模层中的间隔物材料中形成具有大于线的宽度的线和逻辑器件部件的特征。

6. 发明授权

US06410440B1 Method and apparatus for a gaseous environment providing improved control of CMP process 有权
标题翻译：用于气体环境的方法和装置，提供对CMP工艺的改进的控制
公开(公告)号：US06410440B1
公开(公告)日：2002-06-25
申请号：US09305977
申请日：1999-05-05
申请人： Charles F. Drill , Milind Weling
发明人： Charles F. Drill , Milind Weling
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , B24B37/042 , H01L21/31053
摘要： A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad. Another step provides a blanket of gas that displaces the ambient atmosphere surrounding the semiconductor wafer. In another step, the blanket of gas is maintained around the semiconductor wafer during the CMP operation.
摘要翻译：一种使用气体环境提供改进的CMP工艺控制的方法。在一个实施例中，该方法包括几个步骤。一步涉及将半导体晶片放置在CMP机器的抛光垫上。随后的步骤将浆料分配到抛光垫上。另一个步骤提供了一个气体覆盖物，其覆盖半导体晶片周围的环境大气。在另一步骤中，在CMP操作期间，气体保护层保持在半导体晶片周围。

7. 发明授权

US06353261B1 Method and apparatus for reducing interconnect resistance using an interconnect well 失效
标题翻译：使用互连阱降低互连电阻的方法和装置
公开(公告)号：US06353261B1
公开(公告)日：2002-03-05
申请号：US09303891
申请日：1999-05-03
申请人： Milind Weling
发明人： Milind Weling
IPC分类号： H01L2348
CPC分类号： H01L23/522 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Integrated Circuit (IC). The interconnect well is coupled to the interconnect line and is insulated from other conductive materials in the first circuit layer, and in the plurality of subsequent adjacent layers. The interconnect well has a depth in said multilayered IC that exceeds said depth of said interconnect line.
摘要翻译：一种使用优化沟槽几何形状降低互连电阻的设备。一个实施例包括互连线和互连阱。由导电材料构成的互连线具有深度并存在于多层集成电路（IC）的第一电路层中。互连阱耦合到互连线，并且与第一电路层中的其它导电材料以及多个随后的相邻层绝缘。互连阱在所述多层IC中具有超过所述互连线的所述深度的深度。

8. 发明授权

US5399533A Method improving integrated circuit planarization during etchback 失效
标题翻译：在回蚀期间改进集成电路平面化的方法
公开(公告)号：US5399533A
公开(公告)日：1995-03-21
申请号：US161642
申请日：1993-12-01
申请人： Dipankar Pramanik , Vivek Jain , Milind Weling
发明人： Dipankar Pramanik , Vivek Jain , Milind Weling
IPC分类号： H01L21/768 , H01R , H01R4/64
CPC分类号： H01L21/76819
摘要： An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto. A second metal layer is deposited on the oxide layer and the fabrication process continues until the integrated circuit is complete.
摘要翻译：集成电路制造方法从形成在衬底上的半导体器件开始。图案化的金属层沉积在衬底上以连接半导体器件。氮化物层沉积在金属层和衬底上。氮化物层形貌包括位于非金属区域上的金属区域和山谷之上的山丘。旋转玻璃（SOG）沉积在氮化物层上，从而填充谷并覆盖山丘。使用等离子体蚀刻以基本相同的蚀刻速率回蚀SOG层和氮化物层丘，以形成平坦表面。然后在平面表面上沉积氧化物层以封装半导体器件，金属层，氮化物层和SOG层。然后可以将通孔蚀刻通过氧化物层和氮化物层以暴露下面的金属层的部分，并促进与其的上层金属连接。第二金属层沉积在氧化物层上，制造过程继续进行，直到集成电路完成。

9. 发明授权

US06319796B1 Manufacture of an integrated circuit isolation structure 有权
标题翻译：制造集成电路隔离结构
公开(公告)号：US06319796B1
公开(公告)日：2001-11-20
申请号：US09377043
申请日：1999-08-18
申请人： Olivier Laparra , Ramiro Solis , Hunter Brugge , Michela S. Love , Bijan Moslehi , Milind Weling
发明人： Olivier Laparra , Ramiro Solis , Hunter Brugge , Michela S. Love , Bijan Moslehi , Milind Weling
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S148/05
摘要： Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.
摘要翻译：公开了提供集成电路的技术，包括提供改进的集成电路隔离结构。这些技术包括在集成电路衬底中形成多个沟槽以限定要彼此电绝缘的多个衬底区域。通过暴露于具有第一沉积到蚀刻比的高密度等离子体，在沟槽中沉积电介质材料。将高密度等离子体调整到大于第一比率的第二沉积蚀刻比，以在至少部分地填充沟槽之后在基板上积累电介质材料。去除介电材料的一部分以使工件平坦化。可以随后在沟槽之间的衬底区域中形成多个组件，例如绝缘栅场效应晶体管。

10. 发明授权

US06193860B1 Method and apparatus for improved copper plating uniformity on a semiconductor wafer using optimized electrical currents 有权
标题翻译：使用优化的电流在半导体晶片上改善镀铜均匀性的方法和装置
公开(公告)号：US06193860B1
公开(公告)日：2001-02-27
申请号：US09298629
申请日：1999-04-23
申请人： Milind Weling
发明人： Milind Weling
IPC分类号： C25B904
CPC分类号： C25D17/12 , C25D7/12 , C25D17/001 , C25D21/12
摘要： An apparatus for optimizing electrical currents to improve copper plating uniformity on a semiconductor wafer is disclosed. The use of multiple anodes of the embodiment provides for variable electrical currents to the semiconductor wafer, the variable feature of the variable electrical currents compensating for non-uniform electroplating characteristics.
摘要翻译：公开了一种用于优化电流以提高半导体晶片上的镀铜均匀性的装置。本实施例的多个阳极的使用提供了对半导体晶片的可变电流，可变电流的可变特征补偿了不均匀的电镀特性。

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