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1. 发明授权

US09490256B2 Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes and method of manufacturing the same 有权
标题翻译：具有与相关的位线结构和接触孔重叠的接触插塞的半导体器件及其制造方法
公开(公告)号：US09490256B2
公开(公告)日：2016-11-08
申请号：US14754040
申请日：2015-06-29
申请人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
发明人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L21/76879 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
摘要翻译：半导体器件可以包括根据衬底上的布局布置的多个着陆焊盘，其中每个着陆焊盘的横截面形状具有菱形形状，使得菱形形状的相对内部角度彼此相等，并且钻石形状的相邻内角彼此不相等。

2. 发明申请

US20160056159A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS OVERLAPPING ASSOCIATED BITLINE STRUCTURES AND CONTACT HOLES AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触片的半导体器件重叠相关的位线结构和接触孔及其制造方法
公开(公告)号：US20160056159A1
公开(公告)日：2016-02-25
申请号：US14754040
申请日：2015-06-29
申请人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
发明人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
IPC分类号： H01L27/108 , H01L23/535
CPC分类号： H01L27/10885 , H01L21/76879 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
摘要翻译：半导体器件可以包括根据衬底上的布局布置的多个着陆焊盘，其中每个着陆焊盘的横截面形状具有菱形形状，使得菱形形状的相对内部角度彼此相等，并且钻石形状的相邻内角彼此不相等。

3. 发明授权

US07511328B2 Semiconductor device having raised cell landing pad and method of fabricating the same 失效
标题翻译：具有升高电池着陆垫的半导体器件及其制造方法
公开(公告)号：US07511328B2
公开(公告)日：2009-03-31
申请号：US11268551
申请日：2005-11-08
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： H01L27/108
CPC分类号： H01L27/10855 , H01L21/76895
摘要： A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
摘要翻译：半导体器件及其制造方法具有焊盘延伸部分，该半导体器件包括限定有源区的隔离层和穿过有源区的栅电极。源极区域设置在栅电极的一侧的有源区中，并且在栅电极的第二侧的有源区中设置有漏极区。第一层间绝缘层覆盖半导体衬底。源着陆焊盘电连接到源极区域，并且漏极接地焊盘电连接到漏极区域。垫片延伸部分层压在源着陆垫和排水着陆垫的一个或多个上。焊盘延伸部分具有位于与源着陆焊盘和排水接地焊盘的上表面对应的平面上方的平面中的上表面。

4. 发明授权

US07495022B2 α,β-unsaturated hydroxamic acid derivatives and their use as histone deacetylase inhibitors 有权
标题翻译： α，β-不饱和异羟肟酸衍生物及其作为组蛋白脱乙酰酶抑制剂的用途
公开(公告)号：US07495022B2
公开(公告)日：2009-02-24
申请号：US10510630
申请日：2003-04-10
申请人： Dae-Kee Kim , Ju Young Lee , Nam Kyu Lee , Jae-Sun Kim , Junwon Lee , Suk Ho Lee , Jin Young Choi , Je Ho Ryu , Nam Ho Kim , Guang-Jin Im , Tae Kon Kim , Jung-Woo Seo , Young-Jue Bang
发明人： Dae-Kee Kim , Ju Young Lee , Nam Kyu Lee , Jae-Sun Kim , Junwon Lee , Suk Ho Lee , Jin Young Choi , Je Ho Ryu , Nam Ho Kim , Guang-Jin Im , Tae Kon Kim , Jung-Woo Seo , Young-Jue Bang
IPC分类号： A61K31/19 , C07D207/32
CPC分类号： C07D213/82 , C07C259/06 , C07C317/44 , C07D213/38 , C07D213/71 , C07D213/81 , C07D215/48 , C07D215/54 , C07D295/155
摘要： Disclosed are agents that inhibit histone deacetylase. More specifically, the present invention relates to novel hydroxamic acid derivatives or pharmaceutically acceptable salts thereof for anticancer agents or other therapeutic agents based on their histone deacetylase inhibitory activity.
摘要翻译：公开了抑制组蛋白脱乙酰酶的药剂。更具体地，本发明涉及用于抗癌剂或其它治疗剂的新型异羟肟酸衍生物或其药学上可接受的盐，基于其组蛋白脱乙酰酶抑制活性。

5. 发明授权

US07919127B2 Pulsatilla spp. extracts effective in brain function 有权
标题翻译：白头翁属提取有效的脑功能
公开(公告)号：US07919127B2
公开(公告)日：2011-04-05
申请号：US11883612
申请日：2005-02-03
申请人： Wonrack Choi , Chang-Kyun Han , Jung-Woo Seo , Guang-Jin Im , ChilMann Jung , Se Jun Yun , Wie-Jong Kwak , Tae Kon Kim , bongcheol Kim , Soomin Lee
发明人： Wonrack Choi , Chang-Kyun Han , Jung-Woo Seo , Guang-Jin Im , ChilMann Jung , Se Jun Yun , Wie-Jong Kwak , Tae Kon Kim , bongcheol Kim , Soomin Lee
IPC分类号： A61K36/00
CPC分类号： A61K36/71
摘要： This invention relates to Pulsatillae Radix extract for improving brain functions. More specifically, this invention relates to Pulsatillae Radix extract, its active fractions and a pharmaceutical product and a health food containing the same respectively having a protective activity against neurotoxicity and a growth inhibitory effect induced by beta-amyloid, an anti-oxidizing effect, a neuron proliferating effect and improving memory thereby effective in improving brain functions such as Mild Cognitive Impairment and dementia.
摘要翻译：本发明涉及白头翁提取物，用于改善脑功能。更具体地，本发明涉及白头翁提取物，其活性成分和药物，以及含有分别具有抗神经毒性的保护活性和由β-淀粉样蛋白诱导的生长抑制作用的保健食品的保健食品，抗氧化作用，神经元增殖效应和提高记忆力，从而有效改善脑功能，如轻度认知障碍和痴呆。

6. 发明申请

US20060146595A1 Methods for forming DRAM devices including protective patterns and related devices 失效
标题翻译：用于形成包括保护图案和相关装置的DRAM装置的方法
公开(公告)号：US20060146595A1
公开(公告)日：2006-07-06
申请号：US11327067
申请日：2006-01-06
申请人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
发明人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
IPC分类号： G11C11/00
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10855
摘要： A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
摘要翻译：在半导体衬底上形成第一层间电介质。接触焊盘被形成为通过第一层间电介质接触衬底。在第一层间电介质上形成位线不接触接触垫。形成第二层间电介质并将其平坦化以暴露位线的顶部。在所得结构的整个表面上形成保护层。在保护层上形成牺牲层。牺牲层，保护层和第二层间电介质在两个相邻的位线之间被图案化以形成露出接触焊盘的底部电极接触孔。形成导电层并平坦化以形成填充底部电极接触孔的底部电极接触塞。

7. 发明申请

US20060222966A1 Mask layout and method of forming contact pad using the same 失效
标题翻译：使用其形成接触垫的掩模布局和方法
公开(公告)号：US20060222966A1
公开(公告)日：2006-10-05
申请号：US11342560
申请日：2006-01-31
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： H01L21/31144 , G03F1/00 , H01L21/76897
摘要： Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
摘要翻译：提供了使用这种光掩模的接触光掩模和方法来制造半导体器件，并在暴露在栅极线之间的有源区域的部分上形成接触插塞。细长的有源区域被排列成一系列平行的组，每个组又沿它们的纵向轴线对准，以与栅极线形成锐角。接触光掩模包括以平行线布置的多个开口，其以与先前形成的栅极线偏移的角度排列，并且可以平行于有源区域，或者可以与两个活动组的轴线偏移的角度对准区域和栅极线。使用这种光掩模形成接触塞的方法可以提供增加的加工余量，并且扩展了展示增加的集成密度和/或构建到更苛刻的设计规则的半导体器件的常规曝光设备的效用。

8. 发明申请

US20090072418A1 MANUFACTURING THIN-FILM TRANSISTOR AND COLOR FILTER SUBSTRATES 审中-公开
标题翻译：制造薄膜晶体管和彩色滤光片基板
公开(公告)号：US20090072418A1
公开(公告)日：2009-03-19
申请号：US12048124
申请日：2008-03-13
申请人： Jae-Hyuk Chang , Jung-Woo Seo , Jung-Woo Park , Jung-Woo Cho
发明人： Jae-Hyuk Chang , Jung-Woo Seo , Jung-Woo Park , Jung-Woo Cho
IPC分类号： B29D11/00 , B29C35/08
CPC分类号： B29D11/00634 , B29C59/022 , B29C2059/023 , G02F1/133516 , G02F1/1362
摘要： A method of manufacturing thin film transistor and color filter substrates suitable for liquid crystal displays comprises imprinting a pattern in a resin layer formed on a substrate by disposing a mold on the resin layer, aligning the mold and the substrate, curing an edge portion of the resin layer, pressing the full area of the resin layer, curing the full area of the resin layer, and separating the mold from the resin layer.
摘要翻译：制造适用于液晶显示器的薄膜晶体管和彩色滤光片基板的方法包括：通过在树脂层上设置模具，将模具对准模具和基板，使模具和基板的边缘部分固化，将图案压印在形成在基板上的树脂层中树脂层，按压树脂层的整个区域，固化树脂层的整个区域，并将模具与树脂层分离。

9. 发明申请

US20060138561A1 Semiconductor device having raised cell landing pad and method of fabricating the same 失效
公开(公告)号：US20060138561A1
公开(公告)日：2006-06-29
申请号：US11268551
申请日：2005-11-08
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： H01L29/76 , H01L21/44
CPC分类号： H01L27/10855 , H01L21/76895
摘要： A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.

10. 发明申请

US20060134875A1 Method of forming storage node of capacitor 审中-公开
标题翻译：形成电容器存储节点的方法
公开(公告)号：US20060134875A1
公开(公告)日：2006-06-22
申请号：US11284389
申请日：2005-11-21
申请人： Tae-Hyuk Ahn , Jung-Woo Seo
发明人： Tae-Hyuk Ahn , Jung-Woo Seo
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10894 , H01L28/65
摘要： A method of forming a storage node of a capacitor includes defining a cell region and a peripheral circuit region in a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate of the cell region and the peripheral circuit region. Buried contact plugs are formed to penetrate the interlayer insulating layer of the cell region. A molding layer is formed on the semiconductor substrate of the cell region and the peripheral circuit region. The molding layer of the cell region is patterned, thereby forming storage node holes exposing the buried contact plugs. A conformal storage node layer is formed on the semiconductor substrate having the storage node holes. A photosensitive layer is formed on the semiconductor substrate having the storage node layer. At this time, the photosensitive layer in the cell region is lower in height than the photosensitive layer in the peripheral circuit region. The semiconductor substrate is exposed using a reticle having a scattering bar. The scattering bar of the reticle is positioned to correspond with the cell region. An exposed portion of the photosensitive layer is removed by developing the semiconductor substrate, thereby partially exposing the storage node layer. The photosensitive layer in the storage node holes is therefore maintained. An etch-back is performed on the semiconductor substrate having the exposed storage node layer, thereby separating storage nodes.
摘要翻译：形成电容器的存储节点的方法包括限定半导体衬底中的单元区域和外围电路区域。在单元区域和外围电路区域的半导体衬底上形成层间绝缘层。形成埋入式接触插塞以穿透电池区域的层间绝缘层。在单元区域和外围电路区域的半导体基板上形成成型层。对单元区域的成型层进行图案化，从而形成露出埋入式接触插塞的存储节点孔。在具有存储节点孔的半导体衬底上形成保形存储节点层。在具有存储节点层的半导体衬底上形成感光层。此时，单元区域中的感光层的高度比外围电路区域中的感光层低。使用具有散射棒的掩模版来曝光半导体衬底。掩模版的散射棒被定位成与单元区域对应。通过显影半导体衬底去除感光层的曝光部分，从而部分地曝光存储节点层。因此，保持存储节点孔中的感光层。在具有暴露的存储节点层的半导体衬底上进行回蚀，由此分离存储节点。

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