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1. 发明授权

US09490256B2 Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes and method of manufacturing the same 有权
标题翻译：具有与相关的位线结构和接触孔重叠的接触插塞的半导体器件及其制造方法
公开(公告)号：US09490256B2
公开(公告)日：2016-11-08
申请号：US14754040
申请日：2015-06-29
申请人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
发明人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L21/76879 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
摘要翻译：半导体器件可以包括根据衬底上的布局布置的多个着陆焊盘，其中每个着陆焊盘的横截面形状具有菱形形状，使得菱形形状的相对内部角度彼此相等，并且钻石形状的相邻内角彼此不相等。

2. 发明申请

US20160056159A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS OVERLAPPING ASSOCIATED BITLINE STRUCTURES AND CONTACT HOLES AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触片的半导体器件重叠相关的位线结构和接触孔及其制造方法
公开(公告)号：US20160056159A1
公开(公告)日：2016-02-25
申请号：US14754040
申请日：2015-06-29
申请人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
发明人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
IPC分类号： H01L27/108 , H01L23/535
CPC分类号： H01L27/10885 , H01L21/76879 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
摘要翻译：半导体器件可以包括根据衬底上的布局布置的多个着陆焊盘，其中每个着陆焊盘的横截面形状具有菱形形状，使得菱形形状的相对内部角度彼此相等，并且钻石形状的相邻内角彼此不相等。

3. 发明授权

US08507353B2 Method of forming semiconductor device having self-aligned plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US08507353B2
公开(公告)日：2013-08-13
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

4. 发明授权

US07989279B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07989279B2
公开(公告)日：2011-08-02
申请号：US12136626
申请日：2008-06-10
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

5. 发明授权

US07659162B2 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07659162B2
公开(公告)日：2010-02-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L21/8242
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上和顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

6. 发明授权

US08772121B2 Phase change memory devices and methods of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08772121B2
公开(公告)日：2014-07-08
申请号：US13443132
申请日：2012-04-10
申请人： Kyu-Man Hwang , Jun-Soo Bae , Sung-Un Kwon , Kwang-Ho Park
发明人： Kyu-Man Hwang , Jun-Soo Bae , Sung-Un Kwon , Kwang-Ho Park
IPC分类号： H01L21/20 , H01L21/8222 , H01L29/02 , H01L47/00 , H01L29/40 , H01L29/768
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1683
摘要： A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.
摘要翻译：一种制造相变存储器件的方法包括：形成下电极层图案和覆盖下电极层图案的绝缘夹层，在绝缘中间层中形成第一开口以露出下电极层图案，在其上形成氧化层图案通过部分地除去氧化物层和下部电极层图案，形成绝缘层，在第一开口的侧壁和下部电极的下方形成氧化物层图案，形成绝缘层，填充第一开口的剩余部分，通过湿蚀刻工艺去除氧化物层图案以形成第二开口，并且在下电极上形成相变材料图案，使得相变材料图案填充第二开口。

7. 发明授权

US08361849B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08361849B2
公开(公告)日：2013-01-29
申请号：US13183574
申请日：2011-07-15
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

8. 发明授权

US07202163B2 Local interconnection method and structure for use in semiconductor device 有权
标题翻译：用于半导体器件的局部互连方法和结构
公开(公告)号：US07202163B2
公开(公告)日：2007-04-10
申请号：US10861863
申请日：2004-06-04
申请人： Sung-Un Kwon , Yong-Sun Ko
发明人： Sung-Un Kwon , Yong-Sun Ko
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76808 , H01L21/76895
摘要： A Local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.
摘要翻译：用于形成本发明的局部互连布线结构方法通过形成公共孔径来减小栅电极的局部互连层和有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径半导体衬底的绝缘膜。形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。然后去除第二蚀刻掩模图案。然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

9. 发明申请

US20070004140A1 Method of manufacturing a non-volatile semiconductor memory device 审中-公开
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20070004140A1
公开(公告)日：2007-01-04
申请号：US11475153
申请日：2006-06-27
申请人： Dae-Hyun Jang , Jae-Seung Hwang , Dae-Youp Lee , Sung-Un Kwon
发明人： Dae-Hyun Jang , Jae-Seung Hwang , Dae-Youp Lee , Sung-Un Kwon
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate structure may include a tunnel oxide layer pattern, a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern. A first photoresist pattern may be formed on the second conductive layer pattern to form a source line which may be formed in a region of the first area by implanting impurities. A second photoresist pattern may be formed on a hard mask layer in the second region of the substrate to form a hard mask pattern on a third conductive layer. The second gate structure having substantially vertical sidewalls may be formed in the second area by etching the third conductive layer using the hard mask pattern.
摘要翻译：在制造包括具有第一栅极结构的第一区域和具有第二栅极结构的第二区域的非易失性半导体存储器件的方法中，第一栅极结构可以包括隧道氧化物层图案，第一导电层图案，电介质层图案和第二导电层图案。第一光致抗蚀剂图案可以形成在第二导电层图案上以形成可以通过注入杂质形成在第一区域的区域中的源极线。可以在基板的第二区域中的硬掩模层上形成第二光致抗蚀剂图案，以在第三导电层上形成硬掩模图案。具有基本垂直侧壁的第二栅极结构可以通过使用硬掩模图案蚀刻第三导电层而形成在第二区域中。

10. 发明申请

US20110281428A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110281428A1
公开(公告)日：2011-11-17
申请号：US13183574
申请日：2011-07-15
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/28
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

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