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1. 发明申请

US20110144859A1 APPARATUS AND METHOD FOR PREVENTING COLLISION OF VEHICLE 有权
标题翻译：防止车辆撞击的装置和方法
公开(公告)号：US20110144859A1
公开(公告)日：2011-06-16
申请号：US12779221
申请日：2010-05-13
申请人： Jung Hee SUK , Ik Jae CHUN , Chun Gi LYUH , Soon Il YEO , Wook Jin CHUNG , Jeong Hwan LEE , Jae Chang SHIM , Tae Moon ROH
发明人： Jung Hee SUK , Ik Jae CHUN , Chun Gi LYUH , Soon Il YEO , Wook Jin CHUNG , Jeong Hwan LEE , Jae Chang SHIM , Tae Moon ROH
IPC分类号： G08G1/16 , G06K9/00 , B62D6/00 , B60K31/00 , B62D15/02
CPC分类号： B62D15/0265 , B60W30/12 , B60W30/18163 , G06K9/00798 , G06K9/00805 , G08G1/16 , G08G1/166 , G08G1/167 , Y02T10/84
摘要： The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle.
摘要翻译：本发明提供一种用于使用周围获取的用户车辆周围的图像信息来预测在与车辆相邻的车道上行驶的另一车辆的移动方向的装置和方法，并且执行当移动时防止用户车辆的碰撞的控制处理使用者车辆的方向与另一车辆的移动方向相交。

2. 发明申请

US20110022767A1 DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR 审中-公开
标题翻译：具有中断控制处理器的DMA控制器
公开(公告)号：US20110022767A1
公开(公告)日：2011-01-27
申请号：US12843801
申请日：2010-07-26
申请人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28 , G06F13/24
CPC分类号： G06F13/32
摘要： Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.
摘要翻译：提供了具有中断控制处理器的直接存储器访问（DMA）控制器，其可以根据用户可修改的控制程序来处理与DMA传输相关的中断。 DMA控制器包括可处理DMA传输相关中断的中断控制处理器和从外围设备发送的DMA请求中断，并通过可由用户修改的控制程序控制DMA通道，从而使DMA通道控制和相关减少由多个DMA数据传输引起的中断处理负载，并且向用户提供DMA控制的DMA通道控制和中断处理的灵活性。

3. 发明申请

US20130156319A1 FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME 审中-公开
标题翻译：特征向量分类器和识别装置使用它
公开(公告)号：US20130156319A1
公开(公告)日：2013-06-20
申请号：US13550833
申请日：2012-07-17
申请人： Chun-Gi LYUH , Ik Jae CHUN , Jung Hee SUK , Sanghun YOON , Tae Moon ROH
发明人： Chun-Gi LYUH , Ik Jae CHUN , Jung Hee SUK , Sanghun YOON , Tae Moon ROH
IPC分类号： G06K9/46
CPC分类号： G06K9/6269
摘要： Provided are a feature vector extractor and a recognition device using the same. The feature vector classifier includes a feature vector extractor configured to generate a feature vector and a normalized value from an input image and output the feature vector and the normalized value; and a feature vector classifier configured to normalize the feature vector based on the normalized value and classify the normalized feature vector to recognize the input image. Thus, during extraction and classification of a feature vector, time required for the extraction and classification and the size of hardware required are significantly reduced.
摘要翻译：提供了一种特征向量提取器和使用其的识别装置。特征向量分类器包括：特征向量提取器，被配置为从输入图像生成特征向量和归一化值，并输出特征向量和归一化值; 以及特征矢量分类器，其被配置为基于归一化值对特征向量进行归一化，并且对归一化特征向量进行分类以识别输入图像。因此，在特征向量的提取和分类期间，提取和分类所需的时间以及所需的硬件的大小显着降低。

4. 发明申请

US20110135191A1 APPARATUS AND METHOD FOR RECOGNIZING IMAGE BASED ON POSITION INFORMATION 审中-公开
标题翻译：基于位置信息识别图像的装置和方法
公开(公告)号：US20110135191A1
公开(公告)日：2011-06-09
申请号：US12779237
申请日：2010-05-13
申请人： Chun Gi LYUH , Ik Jae CHUN , Jung Hee SUK , Tae Moon ROH
发明人： Chun Gi LYUH , Ik Jae CHUN , Jung Hee SUK , Tae Moon ROH
IPC分类号： G06K9/64
CPC分类号： G06K9/00664 , G06K9/00791 , G06K9/6807
摘要： According to the present invention, the amount of computation required for image recognition processing can be reduced by extracting only image recognition learning information for an object that may appear in a region having the geographical property of a current position and comparing the image recognition learning information with ambient-image information.
摘要翻译：根据本发明，通过仅提取可能出现在具有当前位置的地理属性的区域中的对象的图像识别学习信息，可以减少图像识别处理所需的计算量，并将图像识别学习信息与环境影像信息。

5. 发明申请

US20080292001A1 APPARATUS AND METHOD FOR CALCULATING SUM OF ABSOLUTE DIFFERENCES FOR MOTION ESTIMATION OF VARIABLE BLOCK 有权
标题翻译：用于计算可变块运动估计的绝对差异的装置和方法
公开(公告)号：US20080292001A1
公开(公告)日：2008-11-27
申请号：US12105745
申请日：2008-04-18
申请人： Yil Suk YANG , Jung Hee SUK , Chun Gi LYUH , Ik Jae CHUN , Tae Moon ROH , Jong Dae KIM , Ki Chul KIM , Jung Hoon KIM
发明人： Yil Suk YANG , Jung Hee SUK , Chun Gi LYUH , Ik Jae CHUN , Tae Moon ROH , Jong Dae KIM , Ki Chul KIM , Jung Hoon KIM
IPC分类号： H04N7/26
CPC分类号： H04N19/00521 , H04N19/102 , H04N19/122 , H04N19/134 , H04N19/436 , H04N19/57 , H04N19/61 , H04N19/86
摘要： Provided are an apparatus and method for calculating a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to a plurality of current frame macroblocks at a time. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in a plurality of serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.
摘要翻译：提供了一种用于计算能够相对于多个当前帧宏块同时并行计算SAD值的可变块的运动估计的绝对差（SAD）的装置和方法。该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算设置在多个串行当前帧宏块中的至少一个像素的SAD值，本地存储器包括当前帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，以及将数据发送到在PE阵列单元中提供的每个PE，以及用于为在本地提供的数据进行命令的控制器要发送对应于至少一个像素的存储器，其中PE阵列单元中提供的每个PE执行计算。

6. 发明申请

US20120226831A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 审中-公开
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20120226831A1
公开(公告)日：2012-09-06
申请号：US13471236
申请日：2012-05-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

7. 发明申请

US20080129359A1 LOW-POWER CLOCK GATING CIRCUIT 有权
标题翻译：低功率时钟提升电路
公开(公告)号：US20080129359A1
公开(公告)日：2008-06-05
申请号：US11945387
申请日：2007-11-27
申请人： Dae Woo LEE , Yil Suk YANG , Ik Jae CHUN , Chun Gi LYUH , Tae Moon ROH , Jong Dae KIM
发明人： Dae Woo LEE , Yil Suk YANG , Ik Jae CHUN , Chun Gi LYUH , Tae Moon ROH , Jong Dae KIM
IPC分类号： H03K3/356
CPC分类号： H03K3/0375
摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.
摘要翻译：提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用单阈值电压。

8. 发明申请

US20110153878A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 有权
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20110153878A1
公开(公告)日：2011-06-23
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

9. 发明申请

US20090138645A1 SOC SYSTEM 有权
标题翻译： SOC系统
公开(公告)号：US20090138645A1
公开(公告)日：2009-05-28
申请号：US12171397
申请日：2008-07-11
申请人： Ik Jae CHUN , Tae Moon ROH , Jong Dae KIM
发明人： Ik Jae CHUN , Tae Moon ROH , Jong Dae KIM
IPC分类号： G06F13/28
CPC分类号： G06F13/1657 , G06F13/28
摘要： Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.
摘要翻译：提供了一种用于多媒体系统的片上系统（SoC）系统，能够高速传输大量的多媒体数据和处理器来快速控制外围设备。 SoC系统包括一个处理器; 多个外围设备; 多个物理划分的存储器; 用于将控制信号从处理器传送到外围设备和存储器的控制总线; 用于在处理器，外围设备和存储器之间传送数据的数据总线; 用于将控制总线和数据总线耦合到处理器的桥; 耦合到控制总线并控制每个存储器的多个存储器控制器; 耦合到数据总线和控制总线的直接存储器访问（DMA）控制器，并控制外围设备和存储器之间的数据传输; 以及耦合在DMA控制器和存储器控制器之间的矩阵开关，并且能够同时进行多个存储器访问。

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