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1. 发明授权

US09672887B2 Semiconductor memory capable of reading data without accessing memory cell 有权
公开(公告)号：US09672887B2
公开(公告)日：2017-06-06
申请号：US15066851
申请日：2016-03-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hironobu Furuhashi , Masahiko Nakayama , Katsuhiko Hoya
IPC分类号： G11C11/00 , G11C11/16 , G11C7/22 , G11C7/10
CPC分类号： G11C11/1673 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C11/16 , G11C11/161 , G11C11/1675 , G11C11/1693 , G11C11/5607
摘要： According to one embodiment, a semiconductor memory includes a first memory cell stably storing data after a first time from an end of a write operation, a buffer latching the data in the write operation, and a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, where the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.

2. 发明授权

US09646667B2 Semiconductor memory device 有权
公开(公告)号：US09646667B2
公开(公告)日：2017-05-09
申请号：US15065550
申请日：2016-03-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tadashi Miyakawa , Katsuhiko Hoya
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： According to one embodiment, a semiconductor memory device includes: a first active area provided in a semiconductor substrate; a second active area provided in the semiconductor substrate and intersecting with the first active area; a first select transistor comprising a first drain region provided in the first active area and a source region provided in an intersection region of the first and second active areas; a second select transistor comprising a second drain region provided in the second active area and sharing the source region; a word line coupled to gates of the first and second select transistors; and first and second variable resistance elements coupled to the first and second drain regions, respectively.

3. 发明申请

US20160086646A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：US20160086646A1
公开(公告)日：2016-03-24
申请号：US14955479
申请日：2015-12-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuhiko Hoya
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G06F11/1048 , G11C7/1006 , G11C7/1096 , G11C8/14 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C2029/0411 , G11C2211/5615
摘要： A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation.
摘要翻译：根据本实施例的半导体存储装置分别包括对应于位线和字线之间的交点的多个位线，多个字线和多个存储单元，并且包括能够存储数据。多个读出放大器分别对应于位线，并且被配置为经由从相应位线中选择的位线来检测存储在存储单元中的数据。多个读取锁存部分别对应于读出放大器，并且被配置为锁存由对应的读出放大器检测到的数据。多个读取全局数据总线分别连接到读取锁存器部分，并且被配置为在数据读取操作时连续发送由读取锁存器部件锁存的数据。

4. 发明授权

US09424906B2 Timing controller with delay time units for a semiconductor storage device 有权
标题翻译：具有半导体存储设备延迟时间单位的定时控制器
公开(公告)号：US09424906B2
公开(公告)日：2016-08-23
申请号：US14680951
申请日：2015-04-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuyuki Fujita , Katsuhiko Hoya
IPC分类号： G11C11/16 , G11C7/22 , G11C8/18
CPC分类号： G11C11/1693 , G11C7/222 , G11C8/18 , G11C11/16 , G11C11/1653 , G11C11/1673
摘要： A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.
摘要翻译：根据本实施例的半导体存储装置包括分别包括多个存储单元的多个存储单元。数据总线由存储器单元共享并从存储器单元或存储器单元传送数据。定时控制器包括由共享数据总线的存储器单元共享的延迟时间单元。定时控制器被配置为在接收到输入信号之后经过预定的延迟时间之后输出用于驱动存储器单元的控制信号。

5. 发明授权

US09348697B2 Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US09348697B2
公开(公告)日：2016-05-24
申请号：US14196689
申请日：2014-03-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuhiko Hoya
IPC分类号： G11C29/00 , G06F11/10 , H03M13/05 , G11B20/18
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/106 , G11B20/1803 , G11B20/1833 , H03M13/05
摘要： According to one embodiment, a magnetic random access memory includes memory cells, a read circuit, (ECC) circuit, an address register, a flag register, a flag check circuit, and a write back circuit. The memory cells each include a magnetoresistive element. The address register stores the address at which the error has been detected by the ECC circuit. The data register stores corrected data in which the error has been corrected by the ECC circuit. The flag register sets an error flag in association with the address at which the error has been detected by the ECC circuit. The flag check circuit checks whether the error flag is set in the flag register. The write back circuit writes back the data to the memory cell designated by the address corresponding to the error flag.
摘要翻译：根据一个实施例，磁性随机存取存储器包括存储器单元，读取电路（ECC）电路，地址寄存器，标志寄存器，标志检查电路和回写电路。存储单元各自包括磁阻元件。地址寄存器存储由ECC电路检测到错误的地址。数据寄存器存储由ECC电路校正错误的校正数据。标志寄存器与由ECC电路检测到错误的地址相关联地设置错误标志。标志检查电路检查标志寄存器中是否设置了错误标志。写回电路将数据写回由与错误标志对应的地址指定的存储单元。

6. 发明申请

US20140328118A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20140328118A1
公开(公告)日：2014-11-06
申请号：US14334547
申请日：2014-07-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuhiko Hoya
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G06F11/1048 , G11C7/1006 , G11C7/1096 , G11C8/14 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C2029/0411 , G11C2211/5615
摘要： A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation.
摘要翻译：根据本实施例的半导体存储装置分别包括对应于位线和字线之间的交点的多个位线，多个字线和多个存储单元，并且包括能够存储数据。多个读出放大器分别对应于位线，并且被配置为经由从相应位线中选择的位线来检测存储在存储单元中的数据。多个读取锁存部分别对应于读出放大器，并且被配置为锁存由对应的读出放大器检测到的数据。多个读取全局数据总线分别连接到读取锁存器部分，并且被配置为在数据读取操作时连续发送由读取锁存器部件锁存的数据。

7. 发明授权

US09368199B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09368199B2
公开(公告)日：2016-06-14
申请号：US14571004
申请日：2014-12-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tadashi Miyakawa , Katsuhiko Hoya , Mariko Iizuka , Hiroyuki Takenaka
IPC分类号： G11C7/10 , G11C7/08 , G11C5/06 , G11C8/16 , G11C13/00 , G11C11/16
CPC分类号： G11C13/0021 , G11C7/10 , G11C7/1012 , G11C7/1069 , G11C11/165 , G11C11/1653
摘要： A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.
摘要翻译：根据实施例的存储器件包括第一存储单元阵列; 第二存储单元阵列; 以及多路复用器，布置在第一存储单元阵列和第二存储单元阵列之间，多路器控制第一存储单元阵列和第二存储单元阵列。

8. 发明授权

US09236104B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09236104B2
公开(公告)日：2016-01-12
申请号：US14334547
申请日：2014-07-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuhiko Hoya
IPC分类号： G11C11/00 , G11C11/16 , G06F11/10 , G11C7/10 , G11C29/04
CPC分类号： G11C11/1673 , G06F11/1048 , G11C7/1006 , G11C7/1096 , G11C8/14 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C2029/0411 , G11C2211/5615
摘要： A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation.
摘要翻译：根据本实施例的半导体存储装置分别包括对应于位线和字线之间的交点的多个位线，多个字线和多个存储单元，并且包括能够存储数据。多个读出放大器分别对应于位线，并且被配置为经由从相应位线中选择的位线来检测存储在存储单元中的数据。多个读取锁存部分别对应于读出放大器，并且被配置为锁存由对应的读出放大器检测到的数据。多个读取全局数据总线分别连接到读取锁存器部分，并且被配置为在数据读取操作时连续发送由读取锁存器部件锁存的数据。

9. 发明授权

US09626128B2 Semiconductor memory device 有权
公开(公告)号：US09626128B2
公开(公告)日：2017-04-18
申请号：US13931273
申请日：2013-06-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuhiko Hoya
IPC分类号： G06F3/06 , G06F12/16 , G11C11/00 , G11C7/10 , G11C7/22 , G11C8/18 , G06F13/16 , G11C29/04
CPC分类号： G06F3/0688 , G06F3/0622 , G06F3/0629 , G06F13/1668 , G11C7/1006 , G11C7/22 , G11C8/18 , G11C11/005 , G11C2029/0411 , Y02D10/14
摘要： According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array. The first controller is configured to access the first memory circuit by the page size stored in the register, in one of an open page policy and closed page policy.

10. 发明授权

US09501352B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09501352B2
公开(公告)日：2016-11-22
申请号：US14458783
申请日：2014-08-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Katsuhiko Hoya , Yasuyuki Eguchi
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1012 , G06F11/108
摘要： According to one embodiment, an encoder generates a write data parity from write data to memory elements. A decoder corrects an error of read data from the memory elements using a read data parity for the read data and a check matrix. An inverter maintains or inverts all bits of a received input. Calculation by the decoder using the read data, the read data parity, and the check matrix produces a first result when an error is not included in the read data, a second result when an error is included in the read data, a third result when an error is not included in the read data and all bits of the read data are inverted, and a fourth result when an error is included in the read data and all bits of the read data are not inverted.
摘要翻译：根据一个实施例，编码器从写入数据到存储器元件生成写入数据奇偶校验。解码器使用读取数据的读取数据奇偶校验和校验矩阵来校正来自存储器元件的读取数据的错误。反相器保持或反转接收到的输入的所有位。当读取数据中不包括错误时，使用读取数据，读取数据奇偶校验和校验矩阵的解码器进行计算，产生第一个结果，当读取数据中包含错误时的第二个结果，第三个结果读取数据中不包括错误，读取数据的所有位都被反转，而当读取数据中包含错误并且所读取的数据的所有位都不反转时的第四个结果。

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