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    • 4. 发明授权
    • Magnetic random access memory
    • 磁性随机存取存储器
    • US09348697B2
    • 2016-05-24
    • US14196689
    • 2014-03-04
    • KABUSHIKI KAISHA TOSHIBA
    • Katsuhiko Hoya
    • G11C29/00G06F11/10H03M13/05G11B20/18
    • G06F11/1076G06F11/10G06F11/106G11B20/1803G11B20/1833H03M13/05
    • According to one embodiment, a magnetic random access memory includes memory cells, a read circuit, (ECC) circuit, an address register, a flag register, a flag check circuit, and a write back circuit. The memory cells each include a magnetoresistive element. The address register stores the address at which the error has been detected by the ECC circuit. The data register stores corrected data in which the error has been corrected by the ECC circuit. The flag register sets an error flag in association with the address at which the error has been detected by the ECC circuit. The flag check circuit checks whether the error flag is set in the flag register. The write back circuit writes back the data to the memory cell designated by the address corresponding to the error flag.
    • 根据一个实施例,磁性随机存取存储器包括存储器单元,读取电路(ECC)电路,地址寄存器,标志寄存器,标志检查电路和回写电路。 存储单元各自包括磁阻元件。 地址寄存器存储由ECC电路检测到错误的地址。 数据寄存器存储由ECC电路校正错误的校正数据。 标志寄存器与由ECC电路检测到错误的地址相关联地设置错误标志。 标志检查电路检查标志寄存器中是否设置了错误标志。 写回电路将数据写回由与错误标志对应的地址指定的存储单元。
    • 8. 发明授权
    • Integrated servo field for memory device
    • 集成伺服字段用于存储器件
    • US09105289B1
    • 2015-08-11
    • US14515220
    • 2014-10-15
    • Seagate Technology LLC
    • Bruce Douglas Buch
    • G11B5/02G11B5/596G11B5/55
    • G11B20/10388G11B5/5539G11B5/59616G11B5/59627G11B20/1803G11B2020/1222
    • A pattern of features of a storage medium includes first features having a first logical state and second features having a second logical state, wherein a cross track dimension of the first features is different from a cross track dimension of the second features. A transducer of a memory device senses the pattern of features and generates a transducer signal. Read circuitry samples the transducer signal at a frequency of a sampling clock signal and generates a read signal from the sampled transducer signal. Servo electronics includes a demodulator that demodulates at least first and second orthogonal frequency components of the read signal. Timing circuitry synchronizes a phase of the sampling clock signal with a phase of the pattern of features using the first orthogonal frequency component. Position error circuitry generates a signal indicating a cross track positional offset of the transducer relative to the features using the first and second orthogonal frequency components.
    • 存储介质的特征的图案包括具有第一逻辑状态的第一特征和具有第二逻辑状态的第二特征,其中第一特征的交叉轨道尺寸不同于第二特征的交叉轨道尺寸。 存储器件的换能器感测特征的图案并产生换能器信号。 读取电路以采样时钟信号的频率对传感器信号进行采样,并从采样的传感器信号产生读取信号。 伺服电子装置包括解调器,其解调读取信号的至少第一和第二正交频率分量。 定时电路使用第一正交频率分量将采样时钟信号的相位与特征图案的相位同步。 位置误差电路使用第一和第二正交频率分量产生指示换能器相对于特征的交叉轨道位置偏移的信号。
    • 10. 发明授权
    • Data storage device generating redundancy for data path protection of a parity sector
    • 数据存储设备产生用于奇偶校验扇区的数据路径保护的冗余
    • US08671250B2
    • 2014-03-11
    • US13327326
    • 2011-12-15
    • Patrick J. Lee
    • Patrick J. Lee
    • G06F12/06G06F11/08
    • G11B20/1803G06F11/1016
    • A data storage device is disclosed comprising a non-volatile memory. A write command is received comprising a first logical block address (LBA) and first user data, and a second LBA and second user data. The first LBA is mapped to a first physical block address (PBA) for addressing a first memory segment. The second LBA is mapped to a second PBA for addressing a second memory segment. First redundancy is generated in response to the first user data, second redundancy in generated in response to the second user data, and parity data is generated in response to the first and second user data. Third redundancy is generated in response to the parity data and in response to at least one of the first LBA and the first PBA and at least one of the second LBA and the second PBA.
    • 公开了一种包括非易失性存储器的数据存储设备。 接收包括第一逻辑块地址(LBA)和第一用户数据以及第二LBA和第二用户数据的写入命令。 第一个LBA被映射到用于寻址第一个存储器段的第一个物理块地址(PBA)。 第二个LBA映射到第二个PBA,用于寻址第二个内存段。 响应于第一用户数据产生第一冗余,响应于第二用户数据而生成第二冗余,并且响应于第一和第二用户数据生成奇偶校验数据。 响应于奇偶校验数据并且响应于第一LBA和第一PBA中的至少一个以及第二LBA和第二PBA中的至少一个而产生第三冗余。