专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09355685B2 Multi-chip package and memory system 有权
公开(公告)号：US09355685B2
公开(公告)日：2016-05-31
申请号：US14590626
申请日：2015-01-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Naoki Matsunaga
IPC分类号： G11C5/06 , G11C8/12 , G11C5/02 , G11C7/10
CPC分类号： G11C5/06 , G11C5/02 , G11C7/10 , G11C7/1015 , G11C8/12 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

2. 发明授权

US08929117B2 Multi-chip package and memory system 有权
标题翻译：多芯片封装和内存系统
公开(公告)号：US08929117B2
公开(公告)日：2015-01-06
申请号：US13773305
申请日：2013-02-21
申请人： Kabushiki Kaisha Toshiba
发明人： Naoki Matsunaga
IPC分类号： G11C5/02 , G11C5/06 , G11C7/10 , G11C8/12
CPC分类号： G11C5/06 , G11C5/02 , G11C7/10 , G11C7/1015 , G11C8/12 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.
摘要翻译：多芯片封装包括包括第一存储器芯片和第二存储器芯片的第一组存储器芯片，包括至少一个存储器芯片的第二组存储器芯片，耦合第一存储器芯片的第一内部布线系统和将第二存储器芯片配置为接收芯片使能信号的第一终端，将所述至少一个存储器芯片耦合到被配置为接收所述芯片使能信号的第二终端的第二内部布线系统。第一存储器芯片和第二存储器芯片各自包括被配置为存储与存储器芯片相关联的地址的芯片地址存储器区域，以及地址重写模块，被配置为重写与存储器芯片相关联并存储在芯片地址存储区域中的地址响应外部操作。

3. 发明授权

US09390000B2 Memory system in which data is written to memory chips based on a distance from a memory controller 有权
标题翻译：基于与存储器控制器的距离将数据写入存储器芯片的存储器系统
公开(公告)号：US09390000B2
公开(公告)日：2016-07-12
申请号：US13742693
申请日：2013-01-16
申请人： Kabushiki Kaisha Toshiba
发明人： Naoki Matsunaga
IPC分类号： G06F12/02 , G11C5/04
CPC分类号： G06F12/0246 , G06F2212/1032 , G06F2212/1036 , G06F2212/7208 , G06F2212/7211 , G11C5/04
摘要： A memory device includes a substrate, a plurality of nonvolatile memory chips disposed on the substrate, and a memory controller disposed on the substrate. The memory chips may be disposed on the same side or the opposite side of the substrate as the memory controller. The memory controller controls each of the nonvolatile memory chips based on a firmware, where the firmware is written in a nonvolatile memory chip positioned at a location farthest from the memory controller. A write system may perform writing using a binary or single level cell (SLC) recording system in memory chips located closest to the memory controller and a multi-value or multi-level cell (MLC) recording system in memory chips located farthest from the memory controller. A weighting factor may be assigned for each of the nonvolatile memory chips based on the distance from the memory controller.
摘要翻译：存储器件包括衬底，设置在衬底上的多个非易失性存储器芯片和布置在衬底上的存储器控制器。存储器芯片可以设置在与存储器控制器相同的一侧或与衬底相反的一侧上。存储器控制器基于固件来控制每个非易失性存储器芯片，其中固件被写入位于最远离存储器控制器的位置的非易失性存储器芯片中。写系统可以使用位于最靠近存储器控制器的存储器芯片中的二进制或单级单元（SLC）记录系统执行写入，以及位于最远离存储器的存储器芯片中的多值或多级单元（MLC）记录系统控制器。可以基于与存储器控制器的距离为每个非易失性存储器芯片分配加权因子。

4. 发明授权

US09466370B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09466370B2
公开(公告)日：2016-10-11
申请号：US14331893
申请日：2014-07-15
申请人： Kabushiki Kaisha Toshiba
发明人： Naoki Matsunaga
IPC分类号： G11C11/34 , G11C16/06 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/26 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/3404 , G11C16/349 , G11C16/3495 , G11C29/52
摘要： According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.
摘要翻译：根据一个实施例，提供了包括非易失性存储器，监视部分，确定部分和通知处理部分的非易失性半导体存储装置。非易失性存储器包括由字线驱动的多个存储单元和产生要施加到字线的读取电压的电压产生部分。监视部分在执行读取处理时监视多个存储单元的阈值分布的变化，以通过将读取的电压施加到字线来读取来自多个存储器单元的数据。确定部根据监视部的监视结果来判定非易失性存储器的劣化程度。通知处理部根据确定部的确定结果通知非易失性存储器的寿命。

5. 发明授权

US09666299B2 Non-volatile semiconductor storage device 有权
公开(公告)号：US09666299B2
公开(公告)日：2017-05-30
申请号：US15257773
申请日：2016-09-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Naoki Matsunaga
IPC分类号： G11C11/34 , G11C16/34 , G11C11/56 , G11C16/04 , G11C16/06 , G06F3/06 , G11C16/26 , G11C29/52
CPC分类号： G11C16/26 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/3404 , G11C16/349 , G11C16/3495 , G11C29/52
摘要： According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式