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1. 发明授权

US09747988B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09747988B2
公开(公告)日：2017-08-29
申请号：US15403339
申请日：2017-01-11
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda
IPC分类号： G11C16/16 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/30 , H01L27/1157 , H01L27/11582
摘要： When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

2. 发明授权

US08917552B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08917552B2
公开(公告)日：2014-12-23
申请号：US13783360
申请日：2013-03-03
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C16/30 , G11C16/34
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/26 , G11C16/30 , G11C2213/71
摘要： A control circuit for a nonvolatile semiconductor storage device, during a write operation, configures multiple bit lines so that bit lines that are adjacent to select bit lines are nonselect bit lines. The control circuit applies a first voltage to a write bit line that is included in the select bit lines, and also applies a second voltage that is higher than the first voltage, to a write inhibit bit line that is included in the select bit lines. Then, the control circuit applies a third voltage that is higher than the second voltage to the nonselect bit lines. As a result, the control circuit raises the voltage of the write inhibit bit line, while maintaining the write bit line at the first voltage. Next, the control circuit applies a fourth voltage for the write operation to the drain-side select gate line.
摘要翻译：用于非易失性半导体存储装置的控制电路在写入操作期间配置多个位线，使得与选择位线相邻的位线是非选择位线。控制电路将第一电压施加到包括在选择位线中的写入位线，并且还将高于第一电压的第二电压施加到包括在选择位线中的写禁止位线。然后，控制电路将高于第二电压的第三电压施加到非选位线。结果，控制电路提高写禁止位线的电压，同时将写位线保持在第一电压。接下来，控制电路将用于写入操作的第四电压施加到漏极侧选择栅极线。

3. 发明授权

US08861275B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08861275B2
公开(公告)日：2014-10-14
申请号：US14098237
申请日：2013-12-05
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda
IPC分类号： G11C16/04 , H01L27/115 , G11C16/16 , G11C16/08 , G11C5/14 , G11C16/30
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/30 , H01L27/1157 , H01L27/11582
摘要： When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
摘要翻译：当选择性地擦除一个子块时，控制电路在第一子块中将第一电压施加到位线和源极线，并且将比第一电压小的第二电压施加到字线。然后，控制电路将低于第一电压的第三电压施加一定值到漏极侧选择栅极线和源极选择栅极线，从而在第一个子块中执行擦除操作。控制电路在存在于相同的存储块中的第二子块中向选择的子块施加基本上与漏极侧选择栅极线和源极侧选择栅极线的第一电压相同的第四电压，从而不在第二子块中执行擦除操作。

4. 发明授权

US09595337B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09595337B2
公开(公告)日：2017-03-14
申请号：US15275614
申请日：2016-09-26
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda
IPC分类号： G11C16/04 , G11C16/16 , G11C16/08 , G11C16/26
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/30 , H01L27/1157 , H01L27/11582
摘要： When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
摘要翻译：当选择性地擦除一个子块时，控制电路在第一子块中将第一电压施加到位线和源极线，并且将比第一电压小的第二电压施加到字线。然后，控制电路将低于第一电压的第三电压施加一定值到漏极侧选择栅极线和源极选择栅极线，从而在第一个子块中执行擦除操作。控制电路在存在于相同的存储块中的第二子块中向选择的子块施加基本上与漏极侧选择栅极线和源极侧选择栅极线的第一电压相同的第四电压，从而不在第二子块中执行擦除操作。

5. 发明授权

US09484105B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09484105B2
公开(公告)日：2016-11-01
申请号：US14842382
申请日：2015-09-01
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda
IPC分类号： G11C16/04 , G11C16/16 , H01L27/115 , G11C16/14 , G11C5/14 , G11C16/08 , G11C16/30
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/30 , H01L27/1157 , H01L27/11582
摘要： When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

6. 再颁专利

USRE45832E1 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：USRE45832E1
公开(公告)日：2016-01-05
申请号：US14026844
申请日：2013-09-13
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda , Yoshihisa Iwata
IPC分类号： G11C16/00 , G11C16/04 , G11C16/14 , G11C5/02 , G11C7/18 , G11C16/10 , H01L27/115
CPC分类号： G11C16/0483 , G11C5/02 , G11C7/18 , G11C16/10 , G11C16/14 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.
摘要翻译：存储器串包括：第一半导体层，包括沿垂直于衬底的方向延伸的柱状部分; 形成为围绕所述柱状部的侧面的第一电荷存储层; 以及形成为围绕所述第一电荷存储层的第一导电层。第一选择晶体管包括：从柱状部分的顶表面向上延伸的第二半导体层; 形成为包围第二半导体层的侧面的第二电荷存储层; 以及形成为围绕所述第二电荷存储层的第二导电层。非易失性半导体存储装置还包括控制电路，其在从所选择的一个存储器串中读取数据之前，将电荷累积在连接到第一选择晶体管的第一选择晶体管的第二电荷存储层中取消选择一个内存字符串。

7. 发明授权

US09159431B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09159431B2
公开(公告)日：2015-10-13
申请号：US14493413
申请日：2014-09-23
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda
IPC分类号： G11C16/04 , G11C16/14 , G11C16/16 , H01L27/115 , G11C5/14 , G11C16/08 , G11C16/30
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/30 , H01L27/1157 , H01L27/11582
摘要： When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
摘要翻译：当选择性地擦除一个子块时，控制电路在第一子块中将第一电压施加到位线和源极线，并且将比第一电压小的第二电压施加到字线。然后，控制电路将低于第一电压的第三电压施加一定值到漏极侧选择栅极线和源极选择栅极线，从而在第一个子块中执行擦除操作。控制电路在存在于相同的存储块中的第二子块中向选择的子块施加基本上与漏极侧选择栅极线和源极侧选择栅极线的第一电压相同的第四电压，从而不在第二子块中执行擦除操作。

8. 发明授权

US09589648B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09589648B1
公开(公告)日：2017-03-07
申请号：US15061967
申请日：2016-03-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takashi Maeda
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/32 , G11C16/3459 , G11C16/3468
摘要： A semiconductor memory device includes a memory string on a well, the memory string including a memory cell connected in series between first and second select transistors, a bit line and a source line respectively connected to the first and second select transistors, a well line connected to the well, first and second select lines respectively connected to gates of the first and second select transistors, a word line connected to a gate of the memory cell transistor, and a control circuit that performs a write operation on the first select transistor, the write operation including a pre-charge operation of the bit line, in which a first voltage is applied to the word line and the second select line, a second voltage higher than the first voltage to the source line and the well line, and a third voltage higher than the first voltage to the first select line.
摘要翻译：半导体存储器件包括阱上的存储器串，存储串包括串联连接在第一和第二选择晶体管之间的存储单元，分别连接到第一和第二选择晶体管的位线和源极线，分别连接到第一和第二选择晶体管的栅极的阱，第一和第二选择线，连接到存储单元晶体管的栅极的字线和对第一选择晶体管执行写入操作的控制电路，写入操作，其包括将第一电压施加到字线和第二选择线的位线的预充电操作，高于源极线和阱线的第一电压的第二电压，以及第三电压电压高于第一选择线的第一电压。

9. 发明授权

US09412756B2 Nonvolatile semiconductor memory device including pillars buried inside through holes same 有权
标题翻译：非易失性半导体存储器件包括埋入通孔内的柱状物
公开(公告)号：US09412756B2
公开(公告)日：2016-08-09
申请号：US14466620
申请日：2014-08-22
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi Maeda , Yoshihisa Iwata
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L23/528 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.
摘要翻译：在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。分路互连和位互连设置在堆叠体的上方。导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。导电柱由金属或低电阻硅形成。其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。

10. 发明授权

US09053805B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09053805B2
公开(公告)日：2015-06-09
申请号：US14014234
申请日：2013-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takashi Maeda
IPC分类号： G11C7/06 , G11C16/26
CPC分类号： G11C16/26 , G11C7/067 , G11C7/1048 , G11C7/12 , G11C16/30
摘要： A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines, each of which is electrically connected to a string of the memory cells, and a sense module provided for each of the bit lines. Each sense module includes a sense transistor that is configured to turn on and off to indicate whether or not data is stored in a memory cell that is targeted by a reading operation, the sense transistor having a threshold voltage level and a gate that is connected to a sense node, the sense node being connected to a discharge line through a series of transistors including the sense transistor so that prior to a sensing operation the sense node can be discharged to a level that is set in accordance with a threshold voltage thereof.
摘要翻译：半导体存储器件包括多个存储器单元，多个位线，每个位线电连接到存储器单元的串，以及为每个位线提供的感测模块。每个感测模块包括感测晶体管，其被配置为导通和截止以指示数据是否存储在由读取操作所针对的存储单元中，所述感测晶体管具有阈值电压电平，以及连接到感测节点，感测节点通过包括感测晶体管的一系列晶体管连接到放电线，使得在感测操作之前，感测节点可以被放电到根据其阈值电压设置的电平。

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