专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060220722A1 Power consumption reduction circuit for clock network 有权
标题翻译：时钟网络功耗降低电路
公开(公告)号：US20060220722A1
公开(公告)日：2006-10-05
申请号：US11220676
申请日：2005-09-08
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： G06F1/04
CPC分类号： G06F1/32 , G06F1/10 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
摘要翻译：一种用于减少由包括传输控制电路的时钟树网络消耗的功率的功耗降低电路。功耗降低电路包括用于控制时钟信号传输到缓冲电路组的传输控制电路，以选择性地提供和中断时钟信号。当传输控制电路中断时钟信号时，开关电路将缓冲电路组与电源断开。

2. 发明申请

US20070195946A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070195946A1
公开(公告)日：2007-08-23
申请号：US11442152
申请日：2006-05-30
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： H04M3/00
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , Y10S257/908 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
摘要翻译：一种半导体集成电路装置，具备包括形成在不同层中的第一潜在电源线和第二潜在电源线的多个电源线层。至少一个电容器接触线从第一和第二电势电源线中的一个延伸到第一和第二电势电源线中的另一个，以便在每个电容器接触线和其周围的线之间形成电容器。

3. 发明授权

US07663175B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07663175B2
公开(公告)日：2010-02-16
申请号：US11442152
申请日：2006-05-30
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , Y10S257/908 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
摘要翻译：一种半导体集成电路装置，具备包括形成在不同层中的第一潜在电源线和第二潜在电源线的多个电源线层。至少一个电容器接触线从第一和第二电势电源线中的一个延伸到第一和第二电势电源线中的另一个，以便在每个电容器接触导线及其周围电线之间形成电容器。

4. 发明授权

US07463076B2 Power consumption reduction circuit for clock network 有权
标题翻译：时钟网络功耗降低电路
公开(公告)号：US07463076B2
公开(公告)日：2008-12-09
申请号：US11220676
申请日：2005-09-08
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： G06F1/04
CPC分类号： G06F1/32 , G06F1/10 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
摘要翻译：一种用于降低由包括传输控制电路的时钟树网络消耗的功率的功耗降低电路。功耗降低电路包括用于控制时钟信号传输到缓冲电路组的传输控制电路，以选择性地提供和中断时钟信号。当传输控制电路中断时钟信号时，开关电路将缓冲电路组与电源断开。

5. 发明授权

US4302361A Pressure sensitive conductor 失效
标题翻译：压敏导体
公开(公告)号：US4302361A
公开(公告)日：1981-11-24
申请号：US15485
申请日：1979-02-26
申请人： Teizo Kotani , Masaki Nagato , Kozo Arai
发明人： Teizo Kotani , Masaki Nagato , Kozo Arai
IPC分类号： H01C10/10 , C08K3/08 , C08K5/057 , H01B1/22 , H01B1/24 , H01B1/04
CPC分类号： H01B1/24 , C08K3/08 , C08K5/057 , H01B1/22
摘要： A pressure sensitive conductor consists essentially of (I) an electrically insulating rubber (excluding addition reaction type liquid silicone rubber), (II) 25 to 50% by volume of electrically conductive metal particles (preferably 40 to 200.mu. in particle size) and (III) 5 to 20% by volume of carbon black, and having a JIS A hardness of at least 40. Said conductor may optionally contain (IV) 0.1 to 5% by volume of a mono-, di- or trialkyl titanate. This pressure sensitive conductor has high mechanical strength, a rapid electrical response to deformations, a low hysteresis of the electrical resistance variation on application and release of pressure, and minimized change of the pressure-resistivity curve under repeated deformations.
摘要翻译：压敏导体基本上由（I）电绝缘橡胶（不包括加成反应型液体硅橡胶）组成，（II）25〜50体积％的导电金属粒子（优选粒径为40〜200μm）和（ III）5至20体积％的炭黑，并且具有至少40的JIS A硬度。所述导体可任选地含有（Ⅳ）0.1至5体积％的钛酸单，二或三烷基酯。该压敏导体具有高的机械强度，对变形的快速电响应，在施加和释放压力时的电阻变化的低滞后，以及在重复变形下压力 - 电阻率曲线的最小化变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式