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1. 发明授权

US08937007B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08937007B2
公开(公告)日：2015-01-20
申请号：US13398254
申请日：2012-02-16
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311 , H01L23/00 , H01L23/31
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

2. 发明申请

US20120149190A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120149190A1
公开(公告)日：2012-06-14
申请号：US13398254
申请日：2012-02-16
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/768
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

3. 发明授权

US08143153B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08143153B2
公开(公告)日：2012-03-27
申请号：US13075463
申请日：2011-03-30
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

4. 发明授权

US07939913B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07939913B2
公开(公告)日：2011-05-10
申请号：US12564989
申请日：2009-09-23
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L23/544 , H01L29/06 , H01L21/768 , H01L21/78
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO2 film; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose the surface of the substrate; a protection film continuously covering the upper surface of the layered body except an electrode pad on the multilayer interconnection structure, and the sidewall and bottom surfaces of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.
摘要翻译：半导体器件包括衬底; 层叠体，其形成在所述基板上并且包括多层互连结构，所述层叠体包括层叠的多层层间绝缘膜，所述层间绝缘膜的介电常数比SiO 2膜低; 在层叠体中连续延伸以防止形成有源元件的器件区域的防潮环; 保护槽部，其在层叠体中的防湿环的外侧连续地形成，以露出基板的表面; 除了多层互连结构上的电极焊盘以及保护槽部分的侧壁和底表面之外，连续地覆盖层叠体的上表面的保护膜; 以及形成在保护膜与保护槽部的侧壁面之间的作为主要成分的Si和C的界面膜。

5. 发明申请

US20110177672A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110177672A1
公开(公告)日：2011-07-21
申请号：US13075463
申请日：2011-03-30
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/762
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

6. 发明申请

US20100006984A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100006984A1
公开(公告)日：2010-01-14
申请号：US12564989
申请日：2009-09-23
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L23/58
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO2 film; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose the surface of the substrate; a protection film continuously covering the upper surface of the layered body except an electrode pad on the multilayer interconnection structure, and the sidewall and bottom surfaces of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.
摘要翻译：半导体器件包括衬底; 层叠体，其形成在所述基板上并且包括多层互连结构，所述层叠体包括层叠的多层层间绝缘膜，所述层间绝缘膜的介电常数比SiO 2膜低; 在层叠体中连续延伸以防止形成有源元件的器件区域的防潮环; 保护槽部，其在层叠体中的防湿环的外侧连续地形成，以露出基板的表面; 除了多层互连结构上的电极焊盘以及保护槽部分的侧壁和底表面之外，连续地覆盖层叠体的上表面的保护膜; 以及形成在保护膜与保护槽部的侧壁面之间的作为主要成分的Si和C的界面膜。

7. 发明授权

US08698279B2 Semiconductor device including capacitor of interconnection 有权
标题翻译：包括互连电容器的半导体器件
公开(公告)号：US08698279B2
公开(公告)日：2014-04-15
申请号：US12958541
申请日：2010-12-02
申请人： Kenichi Watanabe , Nobuhiro Misawa
发明人： Kenichi Watanabe , Nobuhiro Misawa
IPC分类号： H01L23/528 , H01L21/283
CPC分类号： H01L21/76879 , H01L21/76808 , H01L23/5222 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.
摘要翻译：该半导体器件包括：包括彼此堆叠的多个互连层的电容器，多个互连层各自包括沿第一方向延伸的多个电极图案;多个通孔部件，设置在多个互连层之间，并且电连接彼此相邻的互连层之间的多个电极图案，以及形成在多个互连层和多个通孔部之间的绝缘膜。多个通孔部分中的每一个在与第一方向相交的第二方向上布置成从电极图案的中心偏移，并且多个电极图案在通孔部分连接的部分具有较大的线宽，在这些部分，电极图案和相邻电极图案之间的距离减小。

8. 发明申请

US20110133311A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110133311A1
公开(公告)日：2011-06-09
申请号：US12958541
申请日：2010-12-02
申请人： Kenichi Watanabe , Nobuhiro Misawa
发明人： Kenichi Watanabe , Nobuhiro Misawa
IPC分类号： H01L23/528 , H01L21/283
CPC分类号： H01L21/76879 , H01L21/76808 , H01L23/5222 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.
摘要翻译：该半导体器件包括：包括彼此堆叠的多个互连层的电容器，多个互连层各自包括沿第一方向延伸的多个电极图案;多个通孔部件，设置在多个互连层之间，并且电连接彼此相邻的互连层之间的多个电极图案，以及形成在多个互连层和多个通孔部之间的绝缘膜。多个通孔部分中的每一个在与第一方向相交的第二方向上布置成从电极图案的中心偏移，并且多个电极图案在通孔部分连接的部分具有较大的线宽，在这些部分，电极图案和相邻电极图案之间的距离减小。

9. 发明授权

US08791570B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08791570B2
公开(公告)日：2014-07-29
申请号：US13483044
申请日：2012-05-29
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/04
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.
摘要翻译：半导体器件包括嵌入在第一层间绝缘膜中的第一和第二导体图案以及嵌入在第二层间绝缘膜中的第三导体图案，所述第三导体图案包括主要部分和延伸部分，所述延伸部分电连接到第一导体图案通过第一通孔插头，延伸部分具有与第一导体图案相比更靠近主要部分的分支图案，分支图案经由第二通孔插塞与第二导体图案接触，每个主要部分，包括分支图案的延伸部分，第一通孔塞和形成镶嵌结构的第二通孔塞。

10. 发明授权

US08299619B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08299619B2
公开(公告)日：2012-10-30
申请号：US13015594
申请日：2011-01-28
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/40
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure.
摘要翻译：半导体器件具有多层互连结构，其中所述多层互连结构至少包括形成在所述第一互连层上的第一互连层和第二互连层，所述第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案，构成互连图案的一部分和嵌入第一层间绝缘膜中的第二另一互连图案，第二互连层包括嵌入第二层间绝缘膜中并构成所述互连图案的一部分的第三导体图案，第三导体图案的一部分具有延伸部分，以在与第三导体图案相同的层中延伸，第三导体图案经由第一通孔插头在延伸部分的第一区域处电连接到第一导体图案，扩展部分制作ac 通过直径小于第一通孔插头的第二通孔插头，在相对于第一区域进一步远离或接近第三导体图案的第二区域处与第二导体图案接合，第三导体图案的延伸部分导体图案，第一通孔塞和第二通孔塞形式与第二层间绝缘膜一起是双镶嵌结构。

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