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1. 发明申请

US20110177672A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110177672A1
公开(公告)日：2011-07-21
申请号：US13075463
申请日：2011-03-30
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/762
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

2. 发明授权

US07939913B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07939913B2
公开(公告)日：2011-05-10
申请号：US12564989
申请日：2009-09-23
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L23/544 , H01L29/06 , H01L21/768 , H01L21/78
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO2 film; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose the surface of the substrate; a protection film continuously covering the upper surface of the layered body except an electrode pad on the multilayer interconnection structure, and the sidewall and bottom surfaces of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.
摘要翻译：半导体器件包括衬底; 层叠体，其形成在所述基板上并且包括多层互连结构，所述层叠体包括层叠的多层层间绝缘膜，所述层间绝缘膜的介电常数比SiO 2膜低; 在层叠体中连续延伸以防止形成有源元件的器件区域的防潮环; 保护槽部，其在层叠体中的防湿环的外侧连续地形成，以露出基板的表面; 除了多层互连结构上的电极焊盘以及保护槽部分的侧壁和底表面之外，连续地覆盖层叠体的上表面的保护膜; 以及形成在保护膜与保护槽部的侧壁面之间的作为主要成分的Si和C的界面膜。

3. 发明授权

US08937007B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08937007B2
公开(公告)日：2015-01-20
申请号：US13398254
申请日：2012-02-16
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311 , H01L23/00 , H01L23/31
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

4. 发明申请

US20120149190A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120149190A1
公开(公告)日：2012-06-14
申请号：US13398254
申请日：2012-02-16
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/768
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

5. 发明授权

US08143153B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08143153B2
公开(公告)日：2012-03-27
申请号：US13075463
申请日：2011-03-30
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

6. 发明申请

US20100006984A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100006984A1
公开(公告)日：2010-01-14
申请号：US12564989
申请日：2009-09-23
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L23/58
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO2 film; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose the surface of the substrate; a protection film continuously covering the upper surface of the layered body except an electrode pad on the multilayer interconnection structure, and the sidewall and bottom surfaces of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.
摘要翻译：半导体器件包括衬底; 层叠体，其形成在所述基板上并且包括多层互连结构，所述层叠体包括层叠的多层层间绝缘膜，所述层间绝缘膜的介电常数比SiO 2膜低; 在层叠体中连续延伸以防止形成有源元件的器件区域的防潮环; 保护槽部，其在层叠体中的防湿环的外侧连续地形成，以露出基板的表面; 除了多层互连结构上的电极焊盘以及保护槽部分的侧壁和底表面之外，连续地覆盖层叠体的上表面的保护膜; 以及形成在保护膜与保护槽部的侧壁面之间的作为主要成分的Si和C的界面膜。

7. 发明授权

US06440844B1 Semiconductor device with copper wiring and its manufacture method 失效
标题翻译：带铜线的半导体器件及其制造方法
公开(公告)号：US06440844B1
公开(公告)日：2002-08-27
申请号：US09111799
申请日：1998-07-08
申请人： Hideo Takagi , Kiyoshi Izumi , Wataru Futo , Satoshi Otsuka , Shigetaka Uji , Masataka Hoshino , Yukihiro Satoh , Koji Endo , Yuzuru Ohta , Nobuhiro Misawa
发明人： Hideo Takagi , Kiyoshi Izumi , Wataru Futo , Satoshi Otsuka , Shigetaka Uji , Masataka Hoshino , Yukihiro Satoh , Koji Endo , Yuzuru Ohta , Nobuhiro Misawa
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76882 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The method of manufacturing a semiconductor device includes the steps of forming copper wiring; reducing an oxide film on the surface of the copper wiring by heating the copper wiring to a temperature in a range of 250° C.-450° C. under reductive gas or by treating the copper wiring in plasma of reductive gas; and then forming a film of a material not containing oxygen on the copper wiring without exposing the copper wiring to external atmosphere, and can provide a semiconductor device with good copper wiring.
摘要翻译：制造半导体器件的方法包括形成铜布线的步骤; 通过在还原性气体下将铜布线加热到250℃-450℃的温度，或者通过处理还原气体的等离子体中的铜布线来减少铜布线表面上的氧化膜; 然后在铜布线上形成不含氧的材料的膜，而不将铜布线暴露于外部大气，并且可以提供具有良好铜布线的半导体器件。

8. 发明授权

US08791570B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08791570B2
公开(公告)日：2014-07-29
申请号：US13483044
申请日：2012-05-29
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/04
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.
摘要翻译：半导体器件包括嵌入在第一层间绝缘膜中的第一和第二导体图案以及嵌入在第二层间绝缘膜中的第三导体图案，所述第三导体图案包括主要部分和延伸部分，所述延伸部分电连接到第一导体图案通过第一通孔插头，延伸部分具有与第一导体图案相比更靠近主要部分的分支图案，分支图案经由第二通孔插塞与第二导体图案接触，每个主要部分，包括分支图案的延伸部分，第一通孔塞和形成镶嵌结构的第二通孔塞。

9. 发明授权

US08299619B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08299619B2
公开(公告)日：2012-10-30
申请号：US13015594
申请日：2011-01-28
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/40
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure.
摘要翻译：半导体器件具有多层互连结构，其中所述多层互连结构至少包括形成在所述第一互连层上的第一互连层和第二互连层，所述第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案，构成互连图案的一部分和嵌入第一层间绝缘膜中的第二另一互连图案，第二互连层包括嵌入第二层间绝缘膜中并构成所述互连图案的一部分的第三导体图案，第三导体图案的一部分具有延伸部分，以在与第三导体图案相同的层中延伸，第三导体图案经由第一通孔插头在延伸部分的第一区域处电连接到第一导体图案，扩展部分制作ac 通过直径小于第一通孔插头的第二通孔插头，在相对于第一区域进一步远离或接近第三导体图案的第二区域处与第二导体图案接合，第三导体图案的延伸部分导体图案，第一通孔塞和第二通孔塞形式与第二层间绝缘膜一起是双镶嵌结构。

10. 发明申请

US20090294902A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090294902A1
公开(公告)日：2009-12-03
申请号：US12539723
申请日：2009-08-12
申请人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
发明人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
IPC分类号： H01L29/92 , H01L23/525 , H01L21/02
CPC分类号： H01G4/005 , H01G4/228 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.
摘要翻译：半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。电容器元件包括下电极，电介质膜和上电极。下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。电介质膜形成在下电极的上表面和侧表面上。上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。第一层和第二层分别包括第一和第二阻挡金属膜。

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