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    • 3. 发明申请
    • Ferroelectric memory device
    • 铁电存储器件
    • US20050286289A1
    • 2005-12-29
    • US11155032
    • 2005-06-16
    • Kenya Watanabe
    • Kenya Watanabe
    • G11C11/22G11C29/50
    • G11C11/22G11C29/50G11C2029/5002
    • A ferroelectric memory device is characterized in having a first n-type MOS transistor having a gate connected to a word line, a ferroelectric capacitor having one end connected through the first n-type MOS transistor to a bit line, and another end connected to a plate line, and a plate line control circuit that drives the plate line, wherein the plate line control circuit includes an inverter having a first p-type MOS transistor and a second n-type MOS transistor, and an output terminal connected to the plate line, a voltage source that supplies a voltage to be supplied to a source of the first p-type MOS transistor, and a third n-type MOS transistor provided between the voltage source and the output terminal.
    • 铁电存储器件的特征在于具有连接到字线的栅极的第一n型MOS晶体管,具有通过第一n型MOS晶体管连接到位线的一端的铁电电容器,以及连接到 板线和驱动板线的板线控制电路,其中所述板线控制电路包括具有第一p型MOS晶体管和第二n型MOS晶体管的反相器,以及连接到所述板线的输出端子 提供要提供给第一p型MOS晶体管的源极的电压的电压源和设置在电压源和输出端子之间的第三n型MOS晶体管。
    • 4. 发明授权
    • Ferroelectric memory device
    • 铁电存储器件
    • US06947309B2
    • 2005-09-20
    • US10822807
    • 2004-04-13
    • Kenya WatanabeMitsuhiro Yamamura
    • Kenya WatanabeMitsuhiro Yamamura
    • G11C11/22
    • G11C11/22
    • A ferroelectric memory device, in which wordlines and bitlines are hierarchized and influence of disturbance-noise is reduced, includes: first sub-wordline select switches, each of which are disposed between one of the main-wordlines and one end of one of the sub-wordlines provided for the one main-wordline; first sub-bitline select switches, each of which are disposed between one of the main-bitlines and one end of one of the sub-bitlines provided for the one main-bitline; second sub-wordline select switches, each of which are disposed between the other end of one of the sub-wordlines and the unselected wordline potential supply line; and second sub-bitline select switches, each of which are disposed between the other end of one of the sub-bitlines and the unselected bitline potential supply line, each of the first and second sub-wordline select switches and first and second sub-bitline select switches being driven independently at least in one of the sector regions.
    • 其中字线和位线被分级并且干扰噪声的影响减小的铁电存储器件包括:第一子字线选择开关,其中每一个被设置在一个主字线之间,一个子线之一 为一条主要字线提供的文字; 第一子位线选择开关,每个开关分别位于主位线之一和为一个主位线提供的一个子位线的一端之间; 第二子字线选择开关,其中每一个设置在一个子字线的另一端和未选择的字线电位供应线之间; 以及第二子位线选择开关,其中每一个位于第一和第二子字线选择开关和第一和第二子位线之间,每个子位线选择开关设置在子位线之一的另一端和未选择的位线电位供应线之间 至少在一个扇区中选择开关独立驱动。
    • 8. 发明申请
    • ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS
    • 电光设备和电子设备
    • US20120062532A1
    • 2012-03-15
    • US13320041
    • 2010-03-11
    • Kenya Watanabe
    • Kenya Watanabe
    • G09G5/00
    • G09G3/3614G09G2310/0205G09G2310/0283G09G2310/08
    • The electro-optical device includes a first electrode for inverting a polarity, a second electrode opposite to the first electrode, and liquid crystals interposed between these electrodes. Before a polarity inversion timing, the scanning line driver circuit simultaneously selects two or more scanning lines of the plural scanning lines, and the data line driver circuit outputs an offset potential with the polarity opposite to that of the potential of the first electrode thereafter, to a data line. On the other hand, after the polarity inversion timing, the scanning line driver circuit individually selects each of the plural scanning lines, and the data line driver circuit outputs the data potential corresponding to the potential polarity of the first electrode thereafter, to the data line.
    • 电光装置包括用于反转极性的第一电极,与第一电极相对的第二电极和插在这些电极之间的液晶。 在极性反转定时之前,扫描线驱动电路同时选择多条扫描线的两条或更多条扫描线,数据线驱动电路输出与之前的第一电极电位极性相反的偏移电位, 数据线。 另一方面,在极性反转定时之后,扫描线驱动电路分别选择多条扫描线中的每条扫描线,并且数据线驱动电路此后将与第一电极的电位极性对应的数据电位输出到数据线 。
    • 9. 发明授权
    • Ferroelectric memory device
    • 铁电存储器件
    • US07292464B2
    • 2007-11-06
    • US11155032
    • 2005-06-16
    • Kenya Watanabe
    • Kenya Watanabe
    • G11C11/22
    • G11C11/22G11C29/50G11C2029/5002
    • A ferroelectric memory device is characterized in having a first n-type MOS transistor having a gate connected to a word line, a ferroelectric capacitor having one end connected through the first n-type MOS transistor to a bit line, and another end connected to a plate line, and a plate line control circuit that drives the plate line, wherein the plate line control circuit includes an inverter having a first p-type MOS transistor and a second n-type MOS transistor, and an output terminal connected to the plate line, a voltage source that supplies a voltage to be supplied to a source of the first p-type MOS transistor, and a third n-type MOS transistor provided between the voltage source and the output terminal.
    • 铁电存储器件的特征在于具有连接到字线的栅极的第一n型MOS晶体管,具有通过第一n型MOS晶体管连接到位线的一端的铁电电容器,以及连接到 板线和驱动板线的板线控制电路,其中所述板线控制电路包括具有第一p型MOS晶体管和第二n型MOS晶体管的反相器,以及连接到所述板线的输出端子 提供要提供给第一p型MOS晶体管的源极的电压的电压源和设置在电压源和输出端子之间的第三n型MOS晶体管。
    • 10. 发明申请
    • Ferroelectric memory and method of driving the same
    • 铁电记忆及其驱动方法
    • US20060114740A1
    • 2006-06-01
    • US11223600
    • 2005-09-09
    • Kenya Watanabe
    • Kenya Watanabe
    • G11C8/00
    • G11C11/22
    • A ferroelectric memory includes: a memory cell array in which a plurality of memory cells are disposed, a plurality of wordlines, a plurality of platelines, and a plurality of wordline driver circuits; each of the memory cells including a ferroelectric capacitor. A wordline driver circuit circuits includes: a driver DRV which drives a wordline WL; a transfer transistor TRA provided between the driver DRV and the wordline WL; and a gate control circuit. The gate control circuit performs gate control which causes the transfer transistor TRA to be turned on, and performs gate control which causes the transfer transistor TRA to be turned off, before a voltage of the wordline WL is boosted (before a plateline PL is driven) after the transfer transistor TRA has been turned on.
    • 铁电存储器包括:其中设置有多个存储单元的存储单元阵列,多个字线,多个板条和多个字线驱动电路; 每个存储单元包括铁电电容器。 字线驱动器电路电路包括:驱动字线WL的驱动器DRV; 设置在驱动器DRV和字线WL之间的转移晶体管TRA; 和门控电路。 栅极控制电路执行栅极控制,使得传输晶体管TRA导通,并且在字线WL的电压被升高之前(在驱动板线PL之前)执行导致传输晶体管TRA截止的栅极控制, 在转移晶体管TRA已经导通之后。