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1. 发明申请

US20060203542A1 Semiconductor integrated device 有权
标题翻译：半导体集成器件
公开(公告)号：US20060203542A1
公开(公告)日：2006-09-14
申请号：US11341385
申请日：2006-01-30
申请人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
发明人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0047 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor non volatile memory device capable of multiple write operations with high reliability is implemented. The memory device includes memory cells, each comprising a first electrode, a second electrode, and an information storage section put between the two electrodes, wherein an operation to feed a first pulse current from the first electrode to the second, and another operation to feed a second pulse current from the second electrode to the first. A segregation of composing elements of the information storage section is caused by applying the first pulse, however, the segregation of elements is resolved by applying the second pulse, and the composition of the element recovers to the original state.
摘要翻译：实现了具有高可靠性的多次写入操作的半导体非易失性存储器件。存储器件包括存储单元，每个存储单元包括放置在两个电极之间的第一电极，第二电极和信息存储部分，其中将第一脉冲电流从第一电极馈送到第二电极的操作，以及另一个进给从第二电极到第一电极的第二脉冲电流。信息存储部分的组合元件的分离是通过施加第一脉冲引起的，然而，通过应用第二脉冲来解决元件的偏析，并且元件的组成恢复到原始状态。

2. 发明授权

US07443721B2 Semiconductor integrated device 有权
标题翻译：半导体集成器件
公开(公告)号：US07443721B2
公开(公告)日：2008-10-28
申请号：US11341385
申请日：2006-01-30
申请人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
发明人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0047 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor non volatile memory device capable of multiple write operations with high reliability includes memory cells. Each memory cell of the device has a first electrode, a second electrode, and an information storage section between the two electrodes. A segregation of composing elements of the information storage section caused by applying a first current pulse from the first electrode to the second electrode is corrected by applying a second current pulse from the second electrode to the first electrode such that the composition of the storage section recovers to its original state.
摘要翻译：能够具有高可靠性的多次写入操作的半导体非易失性存储器件包括存储单元。器件的每个存储单元具有第一电极，第二电极和两个电极之间的信息存储部分。通过从第二电极向第一电极施加第二电流脉冲来校正由第一电极向第二电极施加第一电流脉冲而引起的信息存储部分的组成元件的分离，使得存储部分的组成恢复到原来的状态。

3. 发明授权

US07379328B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07379328B2
公开(公告)日：2008-05-27
申请号：US11812641
申请日：2007-06-20
申请人： Kenichi Osada , Kiyoo Itoh
发明人： Kenichi Osada , Kiyoo Itoh
IPC分类号： G11C11/00 , G11C5/06 , G11C7/02 , G11C8/00
CPC分类号： H01L27/24 , G11C7/04 , G11C13/0004
摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.
摘要翻译：具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。

4. 发明申请

US20070263433A1 Semiconductor device 有权
公开(公告)号：US20070263433A1
公开(公告)日：2007-11-15
申请号：US11812641
申请日：2007-06-20
申请人： Kenichi Osada , Kiyoo Itoh
发明人： Kenichi Osada , Kiyoo Itoh
IPC分类号： G11C5/06 , G11C11/00 , G11C8/00
CPC分类号： H01L27/24 , G11C7/04 , G11C13/0004
摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

5. 发明授权

US07251157B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07251157B2
公开(公告)日：2007-07-31
申请号：US10933336
申请日：2004-09-03
申请人： Kenichi Osada , Kiyoo Itoh
发明人： Kenichi Osada , Kiyoo Itoh
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C7/04 , G11C13/0004
摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.
摘要翻译：具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。

6. 发明申请

US20090129142A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20090129142A1
公开(公告)日：2009-05-21
申请号：US12357663
申请日：2009-01-22
申请人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
发明人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
IPC分类号： G11C11/00 , H01L27/01
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/108 , H01L27/1203 , Y10S257/903
摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下的层的电位来提高存储单元的性能。提高了处于低功率电压状态的SRAM电路的性能。在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。因此，可以稳定存储单元的操作。

7. 发明授权

US07498637B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US07498637B2
公开(公告)日：2009-03-03
申请号：US11151455
申请日：2005-06-14
申请人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
发明人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/108 , H01L27/1203 , Y10S257/903
摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下的层的电位来提高存储单元的性能。提高了处于低功率电压状态的SRAM电路的性能。在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。因此，可以稳定存储单元的操作。

8. 发明申请

US20050276094A1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US20050276094A1
公开(公告)日：2005-12-15
申请号：US11151455
申请日：2005-06-14
申请人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
发明人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
IPC分类号： G11C11/00 , G11C11/412 , H01L21/8244 , H01L27/108
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/108 , H01L27/1203 , Y10S257/903
摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下的层的电位来提高存储单元的性能。提高了处于低功率电压状态的SRAM电路的性能。在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。因此，可以稳定存储单元的操作。

9. 发明申请

US20050201182A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050201182A1
公开(公告)日：2005-09-15
申请号：US10933336
申请日：2004-09-03
申请人： Kenichi Osada , Kiyoo Itoh
发明人： Kenichi Osada , Kiyoo Itoh
IPC分类号： H01L27/105 , G11C7/00 , H01L27/10 , H01L27/115 , H01L27/24 , H01L45/00
CPC分类号： H01L27/24 , G11C7/04 , G11C13/0004
摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.
摘要翻译：具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。

10. 发明授权

US08427864B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08427864B2
公开(公告)日：2013-04-23
申请号：US13375751
申请日：2010-06-02
申请人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
发明人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
IPC分类号： G11C11/00
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675 , H01L27/228
摘要： To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
摘要翻译：为了在由MOS晶体管和隧道磁阻元件形成的SPRAM的存储单元上写入信息，向存储单元提供与在存储单元上写入信息所需的电流方向相反的方向的电流，然后，为存储单元提供写入所需的电流。以这种方式，即使当相同的信息被顺序地写入存储单元时，由于每当信息被重写时，两个方向上的电流成对地在存储单元的隧道磁阻元件中成对流动，所以，可以抑制隧道磁阻元件的形成。因此，可以提高SPRAM的可靠性。

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