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1. 发明授权

US07881114B2 NAND flash memory device having dummy memory cells and methods of operating same 有权
标题翻译：具有虚拟存储单元的NAND闪存器件及其操作方法
公开(公告)号：US07881114B2
公开(公告)日：2011-02-01
申请号：US12340250
申请日：2008-12-19
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

2. 发明申请

US20100065894A1 Semiconductor Device Having a Field Effect Source/Drain Region 有权
标题翻译：具有场效应源/漏区的半导体器件
公开(公告)号：US20100065894A1
公开(公告)日：2010-03-18
申请号：US12622863
申请日：2009-11-20
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： H01L27/105 , H01L29/772 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

3. 发明授权

US07470948B2 Memory cell array structures in NAND flash memory devices 有权
标题翻译： NAND闪存器件中的存储单元阵列结构
公开(公告)号：US07470948B2
公开(公告)日：2008-12-30
申请号：US11617233
申请日：2006-12-28
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.
摘要翻译： NAND型非易失性半导体存储器件包括在半导体衬底的有源区上的栅极绝缘层，有源区上的第一和第二选择栅极结构以及它们之间的存储栅结构。第一和第二选择栅极结构分别包括多个选择栅极图案，并且存储器栅极结构包括多个存储栅极图案。栅极绝缘层包括多个开口，其中将有源区域的部分暴露在第一和第二选择栅极结构的多个选择栅极图案之间。该器件还可以包括位于栅极图案之间的有源区域的部分中的杂质区域和与栅极绝缘层中的开口暴露的有源区域的部分中的杂质区域相邻的晕圈区域。还讨论了相关的制造方法。

4. 发明授权

US07342827B2 Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same 有权
标题翻译：电荷陷阱型3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US07342827B2
公开(公告)日：2008-03-11
申请号：US11341341
申请日：2006-01-26
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C11/5671
摘要： Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.
摘要翻译：本文公开了一种电荷陷阱型3级非易失性半导体存储器件及其驱动方法。电荷陷阱型3级非易失性半导体存储器件包括存储器阵列，该存储器阵列包括多个存储器元件，每个存储元件能够根据电流的方向存储至少两个电荷陷阱区域中的数据，以及驱动了页缓冲器将三个数据位映射到两个电荷陷阱区域的阈值电压组。电荷陷阱型非易失性半导体存储器件具有每个存储1.5位数据的电荷陷阱区。也就是说，单个存储元件具有用于存储3位数据的电荷陷阱区域，从而在编程和读取操作期间保持高操作速度的同时提高器件集成度。

5. 发明申请

US20070066014A1 Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070066014A1
公开(公告)日：2007-03-22
申请号：US11516541
申请日：2006-09-06
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , G11C11/5621 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/7885 , H01L29/792
摘要： A nonvolatile memory device includes a device isolation layer defining an active region protruding from a semiconductor substrate and an active region separation layer isolating the active region into first and second active regions spaced apart from each other. The active region separation layer is narrower than the device isolation layer. Moreover, the nonvolatile memory device further includes first and second memory cells formed in the first and second active regions, respectively.
摘要翻译：非易失性存储器件包括限定从半导体衬底突出的有源区的器件隔离层和将有源区隔离成彼此间隔开的第一和第二有源区的有源区分离层。有源区分离层比器件隔离层窄。此外，非易失性存储器件还包括分别形成在第一和第二有源区中的第一和第二存储单元。

6. 发明申请

US20070030756A1 Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same 有权
标题翻译：电荷陷阱型3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US20070030756A1
公开(公告)日：2007-02-08
申请号：US11341341
申请日：2006-01-26
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C7/10
CPC分类号： G11C11/5671
摘要： Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.
摘要翻译：本文公开了一种电荷陷阱型3级非易失性半导体存储器件及其驱动方法。电荷陷阱型3级非易失性半导体存储器件包括存储器阵列，该存储器阵列包括多个存储器元件，每个存储元件能够根据电流的方向存储至少两个电荷陷阱区域中的数据，以及驱动了页缓冲器将三个数据位映射到两个电荷陷阱区域的阈值电压组。电荷陷阱型非易失性半导体存储器件具有每个存储1.5位数据的电荷陷阱区。也就是说，单个存储元件具有用于存储3位数据的电荷陷阱区域，从而在编程和读取操作期间保持高操作速度的同时提高器件集成度。

7. 发明授权

US08228738B2 NAND flash memory device having dummy memory cells and methods of operating same 有权
标题翻译：具有虚拟存储单元的NAND闪存器件及其操作方法
公开(公告)号：US08228738B2
公开(公告)日：2012-07-24
申请号：US12977419
申请日：2010-12-23
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

8. 发明授权

US08085607B2 3-level non-volatile semiconductor memory device and method of driving the same 失效
标题翻译： 3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US08085607B2
公开(公告)日：2011-12-27
申请号：US12830464
申请日：2010-07-06
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

9. 发明申请

US20100271873A1 3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME 失效
标题翻译： 3级非挥发性半导体存储器件及其驱动方法
公开(公告)号：US20100271873A1
公开(公告)日：2010-10-28
申请号：US12830464
申请日：2010-07-06
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

10. 发明授权

US07821825B2 NAND flash memory devices having shielding lines between wordlines and selection lines 有权
标题翻译： NAND闪存器件在字线和选择线之间具有屏蔽线
公开(公告)号：US07821825B2
公开(公告)日：2010-10-26
申请号：US12358009
申请日：2009-01-22
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.
摘要翻译：一种对闪速存储器进行编程的方法包括：对至少一个屏蔽线施加屏蔽电压，该屏蔽线介于多个字线和选择线之间，并且可操作以在编程操作期间减小字线和选择线之间的电容耦合，以及通过字线之一向存储器单元施加编程电压。

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