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    • 2. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US08124976B2
    • 2012-02-28
    • US12095663
    • 2006-12-01
    • Koichi TakedaKiyoshi Takeuchi
    • Koichi TakedaKiyoshi Takeuchi
    • H01L27/11
    • H01L21/845H01L27/0207H01L27/11H01L27/1104H01L27/1211Y10S257/903
    • The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor.
    • 本发明提供了包括SRAM单元单元的半导体器件,每个SRAM单元包括由一对驱动晶体管和一对负载晶体管构成的数据保持部分,由一对存取晶体管构成的数据写入部分和数据读取部分 由存取晶体管和驱动晶体管构成,其中每个晶体管包括从基板向上突出的半导体层,从半导体层的顶部延伸到相对侧表面的栅电极,以跨越半导体层, 栅极电极和半导体层之间的栅极绝缘膜以及源极/漏极区域,沿着第一方向设置每个半导体层的纵向方向,并且对于彼此相邻的SRAM单元单元之间的所有对应的晶体管 在第一方向上,一个对应的晶体管中的半导体层位于半导体1a的中心线上 沿另一个晶体管的第一个方向。
    • 6. 发明申请
    • SYSTEM, METHOD AND PROGRAM FOR DETERMINING WORST CONDITION OF CIRCUIT OPERATION
    • 用于确定电路运行条件的系统,方法和程序
    • US20100076741A1
    • 2010-03-25
    • US12527862
    • 2008-02-13
    • Kiyoshi Takeuchi
    • Kiyoshi Takeuchi
    • G06F17/50G06F17/18
    • G06F17/504
    • A system for determining a worst condition, wherein, in a model for which one or more parameters included in a model function that simulates a circuit performance index are random variable(s) to simulate the circuit performance index and fluctuations thereof, the parameter(s) for which the circuit performance index assumes a maximum or minimum value that is to be assumed from the viewpoint of designing is determined as the worst condition; the system comprises a worst condition search unit that searches for a point, having a maximum or minimum value of the circuit performance index, on an equi-probability surface corresponding to a preset good product ration within a space defined by the parameter(s); the point thus searched being determined as the worst condition.
    • 一种用于确定最差状况的系统,其中,在模拟包括在模拟电路性能指标的模型函数中的一个或多个参数的模型中,用于模拟电路性能指标及其波动的随机变量, )将电路性能指标设定为从设计的观点假设的最大值或最小值被确定为最差条件; 所述系统包括最差条件搜索单元,其在具有所述电路性能指标的最大值或最小值的点上,在对应于由所述参数限定的空间内的预设好产品比例的等概率表面上进行搜索; 这样搜索的点被确定为最差条件。
    • 9. 发明申请
    • Field effect transistor and method for producing the same
    • 场效应晶体管及其制造方法
    • US20070158700A1
    • 2007-07-12
    • US10587845
    • 2005-01-28
    • Risho KohKatsuhiko TanakaKiyoshi Takeuchi
    • Risho KohKatsuhiko TanakaKiyoshi Takeuchi
    • H01L29/76
    • H01L29/785H01L29/66795H01L29/66803H01L29/7854H01L29/78609
    • A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first conductivity type impurity is introduced, wherein the semiconductor layer has a channel forming region in a portion sandwiched between the source/drain regions, and has in the upper part of the semiconductor layer in the channel forming region a channel impurity concentration adjusting region of which the concentration of a second conductivity type impurity is higher than that in the lower part of the semiconductor layer, and in the channel impurity concentration adjusting region, a channel is formed in a side surface portion facing the gate insulating film of the semiconductor layer in the channel impurity concentration adjusting region in a state of operation in which a signal voltage is applied to the gate electrode.
    • 一种场效应晶体管,包括:从基底的平面突出的半导体层; 设置在所述半导体层的相对侧表面上的栅电极; 介于栅电极和半导体层的侧表面之间的栅极绝缘膜; 以及引入第一导电型杂质的源极/漏极区域,其中半导体层在夹在源极/漏极区域之间的部分中具有沟道形成区域,并且在沟道形成区域a中的半导体层的上部 沟道杂质浓度调整区域,其中第二导电类型杂质的浓度高于半导体层的下部,并且在沟道杂质浓度调节区域中,在面向栅极绝缘体的侧表面部分中形成沟道 在对栅电极施加信号电压的工作状态下的沟道杂质浓度调整区域中的半导体层的膜。