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1. 发明授权

US09442871B2 Accessing data stored in a command/address register device 有权
标题翻译：访问存储在命令/地址寄存器中的数据
公开(公告)号：US09442871B2
公开(公告)日：2016-09-13
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F13/28 , G06F11/10 , G06F11/16 , G11C29/44 , G06F13/16
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

2. 发明申请

US20160093344A1 METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING 有权
标题翻译：方法，装置和系统来管理隐式预充电指令信号
公开(公告)号：US20160093344A1
公开(公告)日：2016-03-31
申请号：US14498509
申请日：2014-09-26
申请人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
发明人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F13/1668 , G06F13/1689 , G06F21/79 , G11C7/1045 , G11C7/1048 , G11C7/1063 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C11/4094 , Y02D10/14
摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.
摘要翻译：用于在存储器控制器和存储器件之间交换信息的技术和机制。在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。

3. 发明授权

US09053812B2 Fast exit from DRAM self-refresh 有权
标题翻译：快速退出DRAM自刷新
公开(公告)号：US09053812B2
公开(公告)日：2015-06-09
申请号：US13533476
申请日：2012-06-26
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/4076 , G11C2211/4067
摘要： Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.
摘要翻译：本发明的实施例描述了一种动态随机存取存储器（DRAM）装置，其可以中止自刷新模式以改善从自动刷新的DRAM低功率状态的退出时间。在执行自刷新模式期间，DRAM设备可以从可操作地耦合到DRAM设备的存储器控制器接收信号（例如，器件使能信号）。响应于接收到来自存储器控制器的信号，DRAM设备可以中止自刷新模式。

4. 发明授权

US08938573B2 Row hammer condition monitoring 有权
标题翻译：行锤状态监测
公开(公告)号：US08938573B2
公开(公告)日：2015-01-20
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F12/06 , G11C11/406 , G06F11/30
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译：系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。

5. 发明授权

US08806298B2 Reliability, availability, and serviceability in a memory device 有权
标题翻译：内存设备的可靠性，可用性和可维护性
公开(公告)号：US08806298B2
公开(公告)日：2014-08-12
申请号：US12824298
申请日：2010-06-28
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： H03M13/00
CPC分类号： G06F11/1008
摘要： Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.
摘要翻译：本发明的实施例一般涉及提高存储器件的可靠性，可用性和可服务性。在一些实施例中，存储器设备包括具有存储数据位的第一部分的存储器核心和存储对应于数据位的纠错码（ECC）位的第二部分。存储器件还可以包括与存储器核心相同的管芯上的纠错逻辑。在一些实施例中，纠错逻辑使得存储器设备能够计算ECC比特并将所存储的ECC比特与所计算的ECC比特进行比较。

6. 发明申请

US20140089576A1 METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH 有权
标题翻译：方法，提供记忆刷新的装置和系统
公开(公告)号：US20140089576A1
公开(公告)日：2014-03-27
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G06F12/00
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

7. 发明申请

US20140089573A1 METHOD FOR ACCESSING MEMORY DEVICES PRIOR TO BUS TRAINING 审中-公开
标题翻译：用于在总线培训之前访问存储器件的方法
公开(公告)号：US20140089573A1
公开(公告)日：2014-03-27
申请号：US13625673
申请日：2012-09-24
申请人： Palsamy Sakthikumar , Eswaramoorthi Nallusamy , Rahul Khanna , Kuljit S. Bains
发明人： Palsamy Sakthikumar , Eswaramoorthi Nallusamy , Rahul Khanna , Kuljit S. Bains
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： Embodiments of the invention describe apparatuses, systems and methods for enabling memory device access prior to bus training, thereby enabling firmware image storage in non-flash nonvolatile memory, such as DDR DRAM. The increasing size of firmware images, such as BIOS, MRC, and ME firmware, makes current non-volatile storage solutions, such as SPI flash memory, impractical; executing BIOS code in flash is slow, and having a separate non-volatile memory device increases device costs. Furthermore, solutions such as Cache-as-RAM, which are utilized for running the pre-memory BIOS code, are limited by the cache size that is not scalable to the increasing complexity of BIOS code.Embodiments of the invention enable the use of persistent memory, such as DRAM, for BIOS code execution and data transfer by allowing DRAM access before memory channel training; said firmware images may then executed to “train” memory channels for subsequent system use.
摘要翻译：本发明的实施例描述了用于在总线训练之前使存储器件访问的装置，系统和方法，从而使得非易失性存储器（例如DDR DRAM）中的固件图像存储能够实现。诸如BIOS，MRC和ME固件等固件映像的增加使当前的非易失性存储解决方案（如SPI闪存）变得不切实际; 在闪存中执行BIOS代码很慢，并且具有单独的非易失性存储器设备会增加设备成本。此外，用于运行预存储器BIOS代码的诸如Cache-as-RAM的解决方案受到不能随着BIOS代码日益增加的复杂性而变化的高速缓存大小的限制。本发明的实施例能够通过在存储器信道训练之前允许DRAM访问来使用诸如DRAM之类的持久存储器用于BIOS代码执行和数据传输; 所述固件图像然后可以被执行以“训练”存储器通道用于随后的系统使用。

8. 发明申请

US20130117641A1 METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：用于存储器件中的错误管理的方法和系统
公开(公告)号：US20130117641A1
公开(公告)日：2013-05-09
申请号：US13619452
申请日：2012-09-14
申请人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
发明人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1016
摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
摘要翻译：一种用于存储器件中的错误管理的方法和系统。在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

9. 发明授权

US08392650B2 Fast exit from self-refresh state of a memory device 有权
标题翻译：快速退出存储设备的自刷新状态
公开(公告)号：US08392650B2
公开(公告)日：2013-03-05
申请号：US12752918
申请日：2010-04-01
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G06F13/00
CPC分类号： G11C11/40615 , G11C7/22 , G11C7/222 , G11C11/406 , G11C2207/2227 , G11C2211/4067
摘要： A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition.
摘要翻译：系统提供信号以指示存储器件何时退出自刷新。因此，基本上在存储器件退出自刷新的同时（之前或之后），可以触发指示符信号以指示存储器件的正常操作或标准刷新操作和正常存储器访问。存储器控制器可以访问指示符信号以确定存储器件是否处于自刷新状态。因此，存储器控制器可以更仔细地管理向存储器件发送命令的定时，同时减少通常与检测自刷新条件相关联的延迟时间。

10. 发明授权

US08310854B2 Identifying and accessing individual memory devices in a memory channel 有权
标题翻译：识别和访问存储器通道中的各个存储器件
公开(公告)号：US08310854B2
公开(公告)日：2012-11-13
申请号：US13250386
申请日：2011-09-30
申请人： Peter MacWilliams , James Akiyama , Kuljit S. Bains , Douglas Gabel
发明人： Peter MacWilliams , James Akiyama , Kuljit S. Bains , Douglas Gabel
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , G06F13/00
CPC分类号： G06F12/0646
摘要： In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
摘要翻译：在本发明的一个实施例中，提供了存储器集成电路，其包括存储器阵列，寄存器和耦合到寄存器的控制逻辑。存储器集成电路中的存储器阵列存储数据。寄存器包括一个或多个位存储电路以存储一个或多个标识值的同一位。响应于存储在寄存器中的一个或多个同步位，控制逻辑提供对存储器集成电路的独立子通道存储器访问。

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