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1. 发明授权

US07944247B2 Operating circuit 有权
标题翻译：工作电路
公开(公告)号：US07944247B2
公开(公告)日：2011-05-17
申请号：US12417641
申请日：2009-04-03
申请人： Kun-Hsien Li , Chih-Pin Sun , Hao-Ping Hong , Yung-Yu Lin
发明人： Kun-Hsien Li , Chih-Pin Sun , Hao-Ping Hong , Yung-Yu Lin
IPC分类号： H03K5/22
CPC分类号： H03K5/08
摘要： An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.
摘要翻译：操作电路包括差分放大器级，其具有用于接收差分输入的第一输入信号的第一输入节点，用于接收差分输入的第二输入信号的第二输入节点，用于输出第一输出的第一输出节点差分输出的信号和用于输出差分输出的第二输出信号的第二输出节点; 耦合到第一输出节点和第二输出节点的偏移电流级，用于在第一输出节点处感应第一偏移电流，在第二输出节点处引起第二偏移电流; 以及耦合到所述第一输出节点的第一钳位装置，用于根据所述第一输出节点处的所述第一输出信号选择性地钳位所述第一输出节点处的输出电压。

2. 发明申请

US20090251191A1 OPERATING CIRCUIT 有权
标题翻译：操作电路
公开(公告)号：US20090251191A1
公开(公告)日：2009-10-08
申请号：US12417641
申请日：2009-04-03
申请人： Kun-Hsien Li , Chih-Pin Sun , Hao-Ping Hong , Yung-Yu Lin
发明人： Kun-Hsien Li , Chih-Pin Sun , Hao-Ping Hong , Yung-Yu Lin
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.
摘要翻译：操作电路包括差分放大器级，其具有用于接收差分输入的第一输入信号的第一输入节点，用于接收差分输入的第二输入信号的第二输入节点，用于输出第一输出的第一输出节点差分输出的信号和用于输出差分输出的第二输出信号的第二输出节点; 耦合到第一输出节点和第二输出节点的偏移电流级，用于在第一输出节点处感应第一偏移电流，在第二输出节点处引起第二偏移电流; 以及耦合到所述第一输出节点的第一钳位装置，用于根据所述第一输出节点处的所述第一输出信号选择性地钳位所述第一输出节点处的输出电压。

3. 发明授权

US08466594B1 Motor stator 有权
标题翻译：电机定子
公开(公告)号：US08466594B1
公开(公告)日：2013-06-18
申请号：US13372986
申请日：2012-02-14
申请人： Yung-Yu Lin
发明人： Yung-Yu Lin
IPC分类号： H02K3/34
CPC分类号： H02K3/325 , H02K3/522
摘要： A motor stator includes a body member having multiple wire-winding grooves that is formed of a stack of silicon steel plates and defines axially a middle section and two end sections, the wire-dinging grooves in the end sections being greater than in the middle section, two wire racks each having foot tubes respectively inserted into the end sections of the body member in the wire-winding grooves beyond the middle section, the foot tubes having an inner diameter not less than the part of the wire-winding grooves corresponding to the middle section, and insulation sheets having a length greater than the height of the middle section of the body member and being respectively set in the wire-winding grooves and the corresponding foot tubes.
摘要翻译：电动机定子包括主体部件，该主体部件具有由一叠硅钢板形成并具有轴向中间部分和两个端部部分的多个绕线槽，所述端部部分中的焊丝槽大于中间部分每个具有足管的两个线架分别插入超过中间部分的绕线槽中的本体构件的端部部分中，所述脚管具有不小于对应于线圈绕组槽的部分的内径中间部分和绝缘片，其长度大于本体构件的中间部分的高度，并分别设置在线绕槽和相应的脚管中。

4. 发明授权

US08073406B2 Amplitude modulation circuit in polar transmitter and method for calibrating amplitude offset in polar transmitter 有权
标题翻译：极性发射机中的幅度调制电路和极坐标发射机的幅度偏移校准方法
公开(公告)号：US08073406B2
公开(公告)日：2011-12-06
申请号：US12335540
申请日：2008-12-16
申请人： Hsin-Hung Chen , Hsiang-Hui Chang , Chun-Pang Wu , Yung-Yu Lin , Jong-Woei Chen
发明人： Hsin-Hung Chen , Hsiang-Hui Chang , Chun-Pang Wu , Yung-Yu Lin , Jong-Woei Chen
IPC分类号： H03C1/52
CPC分类号： H04B1/04 , H03C5/00 , H04B2001/0491
摘要： An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.
摘要翻译：提供极性发射机中的幅度调制电路和用于校准极性发射机中的振幅偏移的方法。幅度调制电路包括数模转换器（DAC），低通滤波器（LPF），gm级和校准模块。 DAC耦合到幅度调制信号输入端。 LPF耦合到DAC，并且gm级耦合到LPF。校准模块具有耦合到gm级的输入，以及耦合到DAC和gm级之间路径上的节点的输出。该方法包括：根据从gm级产生的幅度调制信号产生振幅偏移校准信号; 以及经由校准模块的输出将幅度偏移校准信号发送到DAC和gm级之间的路径上的节点，以便校准振幅偏移。

5. 发明申请

US20100027537A1 METHOD FOR HANDLING MULTIPLE NETWORK PACKETS 有权
标题翻译：用于处理多个网络分组的方法
公开(公告)号：US20100027537A1
公开(公告)日：2010-02-04
申请号：US12203149
申请日：2008-09-03
申请人： Yung-Yu Lin , Shih-Ting Ou Yang , Yu-Chi Chen
发明人： Yung-Yu Lin , Shih-Ting Ou Yang , Yu-Chi Chen
IPC分类号： H04L12/56
CPC分类号： H04L69/16 , H04L49/901 , H04L69/161 , H04L69/163
摘要： A method for handling multiple network packets is provided. The method is suitable for an embedded system connected to a network, wherein the embedded system includes a network device driver module and a simplified TCP/IP stack module. First, a plurality of network packets are received by the network device driver module. Then, each time when the network device driver module copies one of the network packets into a buffer of the simplified TCP/IP stack module, a packet length of the copied network packet is recorded in a packet information table. Thereafter, the network packets are obtained from the buffer one at a time according to the packet lengths recorded in the packet information table and analyzed by the simplified TCP/IP stack module. Thereby, multiple network packets can be handled correctly even in an environment wherein a simplified TCP/IP stack is used.
摘要翻译：提供了一种处理多个网络数据包的方法。该方法适用于连接到网络的嵌入式系统，其中嵌入式系统包括网络设备驱动器模块和简化的TCP / IP栈模块。首先，由网络设备驱动器模块接收多个网络分组。然后，每当网络设备驱动程序模块将一个网络分组复制到简化的TCP / IP堆栈模块的缓冲器中时，复制的网络分组的分组长度被记录在分组信息表中。此后，根据记录在分组信息表中的分组长度，一次一个地从缓冲器获得网络分组，并通过简化的TCP / IP堆栈模块进行分析。因此，即使在使用简化的TCP / IP堆栈的环境中也可以正确地处理多个网络分组。

6. 发明授权

US07126384B2 Peak detection circuit with double peak detection stages 有权
标题翻译：具有双峰检测级的峰值检测电路
公开(公告)号：US07126384B2
公开(公告)日：2006-10-24
申请号：US10737746
申请日：2003-12-18
申请人： Tse-Hsiang Hsu , Yung-Yu Lin , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Yung-Yu Lin , Chih-Cheng Chen
IPC分类号： H03K5/153
CPC分类号： G01R19/04
摘要： A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.
摘要翻译：具有双峰检测级的峰值检测电路包括模拟峰值检测器，模数转换器（ADC）和数字峰值检测器。模拟峰值检测器接收模拟输入信号，以第一周期检测模拟输入信号的峰值，并输出模拟峰值信号。 ADC接收模拟峰值信号并将其转换为数字信号。数字峰值检测器接收数字信号，以比第一周期长的第二周期检测数字信号的峰值，并输出数字峰值信号。因此，模拟峰值信号由于泄漏而不会严重衰减，数字峰值信号可以长时间保持数字峰值。

7. 发明申请

US20060098557A1 Optical detection system and method to detect storage areas of an optical storage medium 审中-公开
标题翻译：用于检测光学存储介质的存储区域的光学检测系统和方法
公开(公告)号：US20060098557A1
公开(公告)日：2006-05-11
申请号：US11319174
申请日：2005-12-28
申请人： Yung-Yu Lin
发明人： Yung-Yu Lin
IPC分类号： G11B7/00
CPC分类号： G11B7/0053 , G11B7/005 , G11B7/00718 , G11B7/00745
摘要： The present invention is an optical detection system to detect various areas of an optical storage medium. The optical detection system comprises a pickup head, a signal adder and an adding comparator. The pickup head have a light source for providing an incident light beam to the data area and the header, and generating the corresponding reflective light beam. The pickup head detects the reflective light beam to generate left-side detection signals and right-side detection signals. The signal adder adds the amplitudes of the left-side detection signal and the right-side detection signal to generate an adding signal. The adding comparator compares the adding signal with a predetermined adding reference signal to generate a compared adding signal. According to the compared adding signal, the optical detection system can determine that the reflective light beam detected by the pickup head comes from the data area or the header.
摘要翻译：本发明是用于检测光学存储介质的各个区域的光学检测系统。光学检测系统包括拾取头，信号加法器和加法比较器。拾取头具有用于向数据区域和头部提供入射光束的光源，并且生成相应的反射光束。拾取头检测反射光束以产生左侧检测信号和右侧检测信号。信号加法器将左侧检测信号和右侧检测信号的幅度相加以产生相加信号。加法比较器将加法信号与预定的附加参考信号进行比较以产生比较的加法信号。根据比较的加法信号，光学检测系统可以确定由拾取头检测到的反射光束来自数据区或标题。

8. 发明授权

US08121127B2 Method for handling multiple network packets 有权
标题翻译：处理多个网络数据包的方法
公开(公告)号：US08121127B2
公开(公告)日：2012-02-21
申请号：US12203149
申请日：2008-09-03
申请人： Yung-Yu Lin , Shih-Ting Ou Yang , Yu-Chi Chen
发明人： Yung-Yu Lin , Shih-Ting Ou Yang , Yu-Chi Chen
IPC分类号： H04L12/28
CPC分类号： H04L69/16 , H04L49/901 , H04L69/161 , H04L69/163
摘要： A method for handling multiple network packets is provided. The method is suitable for an embedded system connected to a network, wherein the embedded system includes a network device driver module and a simplified TCP/IP stack module. First, a plurality of network packets are received by the network device driver module. Then, each time when the network device driver module copies one of the network packets into a buffer of the simplified TCP/IP stack module, a packet length of the copied network packet is recorded in a packet information table. Thereafter, the network packets are obtained from the buffer one at a time according to the packet lengths recorded in the packet information table and analyzed by the simplified TCP/IP stack module. Thereby, multiple network packets can be handled correctly even in an environment wherein a simplified TCP/IP stack is used.
摘要翻译：提供了一种处理多个网络数据包的方法。该方法适用于连接到网络的嵌入式系统，其中嵌入式系统包括网络设备驱动器模块和简化的TCP / IP栈模块。首先，由网络设备驱动器模块接收多个网络分组。然后，每当网络设备驱动程序模块将一个网络分组复制到简化的TCP / IP堆栈模块的缓冲器中时，复制的网络分组的分组长度被记录在分组信息表中。此后，根据记录在分组信息表中的分组长度，一次一个地从缓冲器获得网络分组，并通过简化的TCP / IP堆栈模块进行分析。因此，即使在使用简化的TCP / IP堆栈的环境中也可以正确地处理多个网络分组。

9. 发明授权

US07675448B1 Continuous-time sigma-delta modulator using dynamic element matching having low latency and dynamic element matching method thereof 有权
标题翻译：具有低延迟的动态元素匹配的连续时间Σ-Δ调制器及其动态元素匹配方法
公开(公告)号：US07675448B1
公开(公告)日：2010-03-09
申请号：US12202339
申请日：2008-09-01
申请人： Sheng-Jui Huang , Yung-Yu Lin
发明人： Sheng-Jui Huang , Yung-Yu Lin
IPC分类号： H03M3/00
CPC分类号： H03M3/338 , H03M1/066 , H03M3/424 , H03M3/464
摘要： In a continuous-time sigma-delta modulator, by using dynamic element matching (DEM) with respect to comparators of a quantizer, or by generating a plurality of candidate DEM results in advance for selecting an approximate DEM result, a time slot for DEM operations in each cycle of a sampling signal is significantly increased without being rushed.
摘要翻译：在连续时间Σ-Δ调制器中，通过相对于量化器的比较器使用动态元件匹配（DEM），或者通过预先生成多个候选DEM结果来选择近似的DEM结果，用于DEM操作的时隙在采样信号的每个周期中，显着增加而不会被冲击。

10. 发明申请

US20100052959A1 CONTINUOUS-TIME SIGMA-DELTA MODULATOR USING DYNAMIC ELEMENT MATCHING HAVING LOW LATENCY AND DYNAMIC ELEMENT MATCHING METHOD THEREOF 有权
标题翻译：使用具有低延迟动态元素匹配的连续时间调制器和动态元件匹配方法
公开(公告)号：US20100052959A1
公开(公告)日：2010-03-04
申请号：US12202339
申请日：2008-09-01
申请人： Sheng-Jui Huang , Yung-Yu Lin
发明人： Sheng-Jui Huang , Yung-Yu Lin
IPC分类号： H03M3/02
CPC分类号： H03M3/338 , H03M1/066 , H03M3/424 , H03M3/464
摘要： In a continuous-time sigma-delta modulator, by using dynamic element matching (DEM) with respect to comparators of a quantizer, or by generating a plurality of candidate DEM results in advance for selecting an approximate DEM result, a time slot for DEM operations in each cycle of a sampling signal is significantly increased without being rushed.
摘要翻译：在连续时间Σ-Δ调制器中，通过相对于量化器的比较器使用动态元件匹配（DEM），或者通过预先生成多个候选DEM结果来选择近似的DEM结果，用于DEM操作的时隙在采样信号的每个周期中，显着增加而不会被冲击。

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