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1. 发明授权

US08552486B2 Forming metal-insulator-metal capacitors over a top metal layer 有权
标题翻译：在顶层金属层上形成金属 - 绝缘体 - 金属电容器
公开(公告)号：US08552486B2
公开(公告)日：2013-10-08
申请号：US13007777
申请日：2011-01-17
申请人： Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
发明人： Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10852 , H01L21/7687 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/53295 , H01L28/10 , H01L28/40 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.
摘要翻译：多个金属层包括顶部金属层。在顶部金属层上设置超厚金属（UTM）层，其中在UTM层和顶部金属层之间不存在额外的金属层。金属 - 绝缘体 - 金属（MIM）电容器设置在UTM层之下和顶部金属层之上。

2. 发明申请

US20120181657A1 Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer 有权
标题翻译：在顶部金属层上形成金属绝缘体金属电容器
公开(公告)号：US20120181657A1
公开(公告)日：2012-07-19
申请号：US13007777
申请日：2011-01-17
申请人： Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
发明人： Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
IPC分类号： H01L29/92
CPC分类号： H01L27/10852 , H01L21/7687 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/53295 , H01L28/10 , H01L28/40 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.
摘要翻译：多个金属层包括顶部金属层。在顶部金属层上设置超厚金属（UTM）层，其中在UTM层和顶部金属层之间不存在额外的金属层。金属 - 绝缘体 - 金属（MIM）电容器设置在UTM层之下和顶部金属层之上。

3. 发明申请

US20050191802A1 Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices 有权
标题翻译：整合浅结N沟道器件的形成与形成P沟道，ESD和输入/输出器件的方法
公开(公告)号：US20050191802A1
公开(公告)日：2005-09-01
申请号：US10788170
申请日：2004-02-26
申请人： Yu-Lung Yeh , Chu-We Hu , Li-Te Hsu , Pin-Chia Su
发明人： Yu-Lung Yeh , Chu-We Hu , Li-Te Hsu , Pin-Chia Su
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/02
CPC分类号： H01L21/823814 , H01L27/0266
摘要： The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The flow of CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.
摘要翻译：已经开发了制造具有浅源极/漏极区域的NMOS器件，其作为用于将其他类型器件的制造与NMOS器件的制造集成的集成工艺序列的一部分进行。集成过程序列的关键特征是在形成其它类型器件之后形成NMOS的浅源/漏区，从而降低了浅源/漏区暴露于用于其他类型的设备。此外，用于去除用于保护完成的其它类型器件免于浅源/漏离子注入过程的光致抗蚀剂形状的方法已被再次修改，以减少对浅源/漏区的可能损坏。在光致抗蚀剂去除等离子体灰化过程期间等离子体工具中的CF 4的流动以及后等离子体灰化湿法清洁程序的长度都被减少，导致浅的源/漏区到这些程序。

4. 发明授权

US06756671B2 Microelectronic device with a redistribution layer having a step shaped portion and method of making the same 失效
标题翻译：具有再分配层的微电子器件具有台阶形部分及其制造方法
公开(公告)号：US06756671B2
公开(公告)日：2004-06-29
申请号：US10190274
申请日：2002-07-05
申请人： Chu-Sheng Lee , Chu-We Hu , Yu-Lung Yeh , Sheng-Hung Chou
发明人： Chu-Sheng Lee , Chu-We Hu , Yu-Lung Yeh , Sheng-Hung Chou
IPC分类号： H01L2348
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/5226 , H01L24/05 , H01L2224/0231 , H01L2224/0233 , H01L2224/02351 , H01L2224/0401 , H01L2224/05556 , H01L2224/05569 , H01L2224/05572 , H01L2224/13099 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.
摘要翻译：一种制造提供具有接合焊盘的基底基板的微电子器件的方法，覆盖基底衬底的第一钝化层和接合焊盘的一部分以及覆盖第一钝化层的第二钝化层; 在所述第二钝化层上形成第一牺牲层，其中所述第一牺牲层包括穿过其的开口; 蚀刻第二钝化层的暴露部分以在其中提供凹陷; 修剪第一牺牲层的一部分以扩大开口; 蚀刻第二钝化层的暴露部分以提供扩大的凹部，第一提升管，第二胎面，第二提升管和第二胎面; 去除第一牺牲层; 将再分布层沉积到第二钝化层中的扩大凹部中，并且在第一提升管，第一胎面，第二提升管和第二胎面之上。

5. 发明授权

US07101748B2 Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices 有权
标题翻译：整合浅结N沟道器件的形成与形成P沟道，ESD和输入/输出器件的方法
公开(公告)号：US07101748B2
公开(公告)日：2006-09-05
申请号：US10788170
申请日：2004-02-26
申请人： Yu-Lung Yeh , Chu-We Hu , Li-Te Hsu , Pin-Chia Su
发明人： Yu-Lung Yeh , Chu-We Hu , Li-Te Hsu , Pin-Chia Su
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/0266
摘要： The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The flow of CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.
摘要翻译：已经开发了制造具有浅源极/漏极区域的NMOS器件，其作为用于将其他类型器件的制造与NMOS器件的制造集成的集成工艺序列的一部分进行。集成过程序列的关键特征是在形成其它类型器件之后形成NMOS的浅源/漏区，从而降低了浅源/漏区暴露于用于其他类型的设备。此外，用于去除用于保护完成的其它类型器件免于浅源/漏离子注入过程的光致抗蚀剂形状的方法已被再次修改，以减少对浅源/漏区的可能损坏。在光致抗蚀剂去除等离子体灰化过程期间等离子体工具中的CF 4的流动以及后等离子体灰化湿法清洁程序的长度都被减少，导致浅的源/漏区到这些程序。

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