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1. 发明授权

US08076235B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08076235B2
公开(公告)日：2011-12-13
申请号：US12913142
申请日：2010-10-27
申请人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
发明人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
IPC分类号： H01L21/768 , H01L21/108 , H01L23/528
CPC分类号： H01L21/76814 , H01L21/76808 , H01L21/76831
摘要： Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.
摘要翻译：半导体器件及其制造方法。这些器件包括衬底，第一蚀刻停止层，电介质层，开口和反扩散层。第一蚀刻停止层覆盖在基底上。介电层覆盖在第一蚀刻停止层上。开口延伸穿过介电层和第一蚀刻停止层，并露出基板的一部分。防扩散层至少覆盖开口的侧壁，防止污染分子从至少第一蚀刻停止层扩散，其中抗扩散层分别比第一蚀刻停止层和电介质层更致密。

2. 发明申请

US20070010085A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070010085A1
公开(公告)日：2007-01-11
申请号：US11176924
申请日：2005-07-07
申请人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
发明人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76808 , H01L21/76831
摘要： Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.
摘要翻译：半导体器件及其制造方法。这些器件包括衬底，第一蚀刻停止层，电介质层，开口和反扩散层。第一蚀刻停止层覆盖在基底上。介电层覆盖在第一蚀刻停止层上。开口延伸穿过介电层和第一蚀刻停止层，并露出基板的一部分。防扩散层至少覆盖开口的侧壁，防止污染分子从至少第一蚀刻停止层扩散，其中抗扩散层分别比第一蚀刻停止层和电介质层更致密。

3. 发明授权

US09373675B2 Capacitor structure and method of forming the same 有权
标题翻译：电容器结构及其形成方法
公开(公告)号：US09373675B2
公开(公告)日：2016-06-21
申请号：US13367064
申请日：2012-02-06
申请人： Tai-Chun Lin , Wen-Tsao Chen , Chih-Ho Tai , Ming-Ray Mao , Kuan-Chi Tsai
发明人： Tai-Chun Lin , Wen-Tsao Chen , Chih-Ho Tai , Ming-Ray Mao , Kuan-Chi Tsai
IPC分类号： H01L29/92 , H01L49/02 , H01L21/3105 , H01L21/02
CPC分类号： H01L28/40 , H01L21/02164 , H01L21/0217 , H01L21/3105
摘要： Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.
摘要翻译：公开的实施例包括电容器结构和形成电容器结构的方法。实施例是在基板上包括导体 - 绝缘体 - 导体电容器的结构。导体 - 绝缘体 - 导体电容器包括在基板上的第一导体，在第一导体上的电介质堆叠，以及位于介电叠层上的第二导体。电介质堆叠包括第一氮化物层，第一氮化物层上的第一氧化物层和第一氧化物层上的第二氮化物层。另一实施例是一种方法，包括在衬底上形成第一导体; 在所述第一导体上形成第一氮化物层; 用第一氧化亚氮（N2O）处理第一氮化物层以在第一氮化物层上形成氧化物层; 在所述氧化物层上形成第二氮化物层; 以及在所述第二氮化物层上形成第二导体。

4. 发明申请

US20130207264A1 Stress Reduction Apparatus 有权
标题翻译：减压装置
公开(公告)号：US20130207264A1
公开(公告)日：2013-08-15
申请号：US13370161
申请日：2012-02-09
申请人： Ying-Ti Lu , Wen-Tsao Chen , Ming-Ray Mao , Kuan-Chi Tsai
发明人： Ying-Ti Lu , Wen-Tsao Chen , Ming-Ray Mao , Kuan-Chi Tsai
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5227 , H01L21/76802 , H01L21/76804 , H01L21/76816 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.
摘要翻译：一种应力降低装置，包括：在基板上形成的金属结构体，在基板上形成的金属间介电层，金属结构体的下部嵌入在金属间介电层内，倒置杯状的应力降低层金属结构，其中金属结构的上部嵌入倒杯形应力减少层中。

5. 发明授权

US07846832B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07846832B2
公开(公告)日：2010-12-07
申请号：US11176924
申请日：2005-07-07
申请人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
发明人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
IPC分类号： H01L21/768 , H01L23/528 , H01L21/108
CPC分类号： H01L21/76814 , H01L21/76808 , H01L21/76831
摘要： Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.
摘要翻译：半导体器件及其制造方法。这些器件包括衬底，第一蚀刻停止层，电介质层，开口和反扩散层。第一蚀刻停止层覆盖在基底上。电介质层覆盖在第一蚀刻停止层上。开口延伸穿过介电层和第一蚀刻停止层，并露出基板的一部分。防扩散层至少覆盖开口的侧壁，防止污染分子从至少第一蚀刻停止层扩散，其中抗扩散层分别比第一蚀刻停止层和电介质层更致密。

6. 发明授权

US08860224B2 Preventing the cracking of passivation layers on ultra-thick metals 有权
标题翻译：防止超厚金属上的钝化层破裂
公开(公告)号：US08860224B2
公开(公告)日：2014-10-14
申请号：US13035517
申请日：2011-02-25
申请人： Yu-Wen Chen , Chuang-Han Hsieh , Kun-Yu Lin , Kuan-Chi Tsai
发明人： Yu-Wen Chen , Chuang-Han Hsieh , Kun-Yu Lin , Kuan-Chi Tsai
IPC分类号： H01L29/06 , H01L23/48 , H01L21/768 , H01L23/528 , H01L23/522
CPC分类号： H01L21/76885 , H01L21/76832 , H01L21/76834 , H01L23/5227 , H01L23/5283 , H01L2224/13 , H01L2924/10158
摘要： A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.
摘要翻译：一种装置包括顶部金属层; 顶部金属层上的UTM线并具有第一厚度; 以及在UTM线上的钝化层并且具有第二厚度。第二厚度与第一厚度的比率小于约0.33。

7. 发明申请

US20120190152A1 Methods for Fabricating Integrated Passive Devices on Glass Substrates 审中-公开
标题翻译：在玻璃基板上制造集成无源器件的方法
公开(公告)号：US20120190152A1
公开(公告)日：2012-07-26
申请号：US13013393
申请日：2011-01-25
申请人： Wen-Chao Chen , Ming-Ray Mao , Shih-Hsien Yang , Kuan-Chi Tsai
发明人： Wen-Chao Chen , Ming-Ray Mao , Shih-Hsien Yang , Kuan-Chi Tsai
IPC分类号： H01L21/02
CPC分类号： H01L24/97 , H01G4/30 , H01G4/306 , H01G4/40 , H01L24/11 , H01L2224/131 , H01L2224/16238 , H01L2224/16268 , H01L2924/14 , H01L2924/15788 , H01L2924/014 , H01L2924/00
摘要： A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers.
摘要翻译：一种方法包括在半导体衬底上形成多个电介质层; 以及在所述多个电介质层中形成集成的无源器件。然后从多个电介质层去除半导体衬底。电介质基板被接合到多个电介质层上。

8. 发明申请

US20110039408A1 Semiconductor Device and Fabrication Method Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110039408A1
公开(公告)日：2011-02-17
申请号：US12913142
申请日：2010-10-27
申请人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
发明人： Kuan-Chi Tsai , Chih-Hsun Lin , Sheng-Wen Su , Shaw-Jang Liou
IPC分类号： H01L21/768
CPC分类号： H01L21/76814 , H01L21/76808 , H01L21/76831
摘要： Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.
摘要翻译：半导体器件及其制造方法。这些器件包括衬底，第一蚀刻停止层，电介质层，开口和反扩散层。第一蚀刻停止层覆盖在基底上。介电层覆盖在第一蚀刻停止层上。开口延伸穿过介电层和第一蚀刻停止层，并露出基板的一部分。抗扩散层至少覆盖开口的侧壁，防止污染分子从至少第一蚀刻停止层扩散，其中抗扩散层分别比第一蚀刻停止层和电介质层更致密。

9. 发明授权

US08629559B2 Stress reduction apparatus with an inverted cup-shaped layer 有权
标题翻译：减压装置具有倒杯形层
公开(公告)号：US08629559B2
公开(公告)日：2014-01-14
申请号：US13370161
申请日：2012-02-09
申请人： Ying-Ti Lu , Wen-Tsao Chen , Ming-Ray Mao , Kuan-Chi Tsai
发明人： Ying-Ti Lu , Wen-Tsao Chen , Ming-Ray Mao , Kuan-Chi Tsai
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5227 , H01L21/76802 , H01L21/76804 , H01L21/76816 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.
摘要翻译：一种应力降低装置，包括：在基板上形成的金属结构体，在基板上形成的金属间介电层，金属结构体的下部嵌入在金属间介电层内，倒置杯状的应力降低层金属结构，其中金属结构的上部嵌入倒杯形应力减少层中。

10. 发明授权

US08552486B2 Forming metal-insulator-metal capacitors over a top metal layer 有权
标题翻译：在顶层金属层上形成金属 - 绝缘体 - 金属电容器
公开(公告)号：US08552486B2
公开(公告)日：2013-10-08
申请号：US13007777
申请日：2011-01-17
申请人： Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
发明人： Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10852 , H01L21/7687 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/53295 , H01L28/10 , H01L28/40 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.
摘要翻译：多个金属层包括顶部金属层。在顶部金属层上设置超厚金属（UTM）层，其中在UTM层和顶部金属层之间不存在额外的金属层。金属 - 绝缘体 - 金属（MIM）电容器设置在UTM层之下和顶部金属层之上。

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