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1. 发明申请

US20120203961A1 HIGH SPEED INTERFACE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权
标题翻译：用于动态随机存取存储器（DRAM）的高速接口
公开(公告)号：US20120203961A1
公开(公告)日：2012-08-09
申请号：US13023991
申请日：2011-02-09
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G06F12/06
CPC分类号： G11C7/10
摘要： An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.
摘要翻译：用于动态随机存取存储器（DRAM）的接口包括使用第一附接结构耦合到DRAM芯片的接口元件，第一附接结构的第一部分用于形成宽带宽，低速并行接口，第二所述第一连接结构的部分，与所述DRAM芯片相关联的路由元件和穿通硅通孔（TSV）用于形成窄带宽高速串行接口，所述接口元件被配置为将并行信息转换为串行信息并配置将串行信息转换为并行信息。

2. 发明申请

US20080266999A1 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM PROVIDING SPARE MEMORY LOCATIONS 有权
标题翻译：半导体存储器件和系统提供备用存储器位置
公开(公告)号：US20080266999A1
公开(公告)日：2008-10-30
申请号：US11739875
申请日：2007-04-25
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G11C8/00
CPC分类号： G11C8/20 , G11C29/70 , G11C29/76
摘要： A semiconductor memory device having a plurality of memory locations is presented. The plurality of memory locations includes a plurality of primary memory locations and a plurality of spare memory locations. The device includes an address decoder configured to receive a memory location address and process the address to select one of the memory locations. The device further includes control logic configured to receive control signals and process the control signals to determine whether the selected one of the memory locations is one of the primary memory locations or one of the spare memory locations, and to provide access to the selected one of the memory locations via data lines.
摘要翻译：提出了具有多个存储位置的半导体存储器件。多个存储器位置包括多个主存储器位置和多个备用存储器位置。该设备包括地址解码器，其被配置为接收存储器位置地址并处理地址以选择存储器位置之一。该设备还包括控制逻辑，其被配置为接收控制信号并处理控制信号以确定所选择的一个存储器位置是主存储器位置之一还是其中一个备用存储器位置，并且提供对所选择的一个通过数据线的存储器位置。

3. 发明授权

US6084601A Corner buffer system for improved memory read efficiency during texture mapping 失效
标题翻译：角缓冲系统，用于在纹理映射期间提高存储器读取效率
公开(公告)号：US6084601A
公开(公告)日：2000-07-04
申请号：US70691
申请日：1998-04-30
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06T15/04
摘要： A corner buffer system for improving memory read efficiency during the process of determining a bilinearly interpolated texel value corresponding to a pixel. The corner buffer system includes a conditional texel quad transposer, a conditional s,t fraction complementer and a corner buffer unit. Addresses for data words corresponding to each texel in a texel quad are received, as well as the two LSBs of the s,t coordinates for at least one of the four texels in the quad. The conditional texel quad transposer routes the texel addresses to first, second, third and fourth outputs according to the values of the LSBs of the s,t coordinates of each texel. The conditional s,t fraction complementer receives the fractional parts of the s,t coordinates of the pixel and conditionally complements them responsive to the state of the LSBs of the s,t coordinates of one of the four texels. The corner buffer unit has four address inputs and includes four sets of address storage registers and data storage registers. Each address input and register set is associated with a corner of the texel quad. At each corner, the address storage register is associated with a corresponding data storage register. Comparators determine, for each corner, whether the address presented at the address input is equal to the address stored for that corner. If they are not equal, texel data corresponding to the non-matching input address is retrieved and stored in the data storage register for that corner.
摘要翻译：一种用于在确定对应于像素的双线性内插纹素值的过程期间提高存储器读取效率的角缓冲器系统。角落缓冲系统包括条件纹理四重转移器，条件s，t分数互补器和拐角缓冲单元。接收与纹理四边形中的每个纹素相对应的数据字的地址以及四边形中的四个纹素中的至少一个的s，t坐标的两个LSB。条件纹理四边形转换器根据每个纹素的s，t坐标的LSB的值将纹素地址路由到第一，第二，第三和第四输出。条件s，t分数补码器接收像素的s，t坐标的小数部分，并根据四个纹素之一的s，t坐标的LSB的状态有条件地补充它们。角落缓冲单元有四个地址输入，包括四组地址存储寄存器和数据存储寄存器。每个地址输入和寄存器集与纹素四边形的一个角相关联。在每个角落，地址存储寄存器与相应的数据存储寄存器相关联。比较器确定每个角落，地址输入中显示的地址是否等于该角落存储的地址。如果它们不相等，则检索对应于不匹配输入地址的纹素数据并将其存储在该角落的数据存储寄存器中。

4. 发明授权

US08886892B2 Memory module and method employing a multiplexer to replace a memory device 有权
标题翻译：存储器模块和采用多路复用器替代存储器件的方法
公开(公告)号：US08886892B2
公开(公告)日：2014-11-11
申请号：US11627469
申请日：2007-01-26
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G06F12/00 , G11C7/00 , G11C8/00 , G11C5/06
CPC分类号： G11C5/066
摘要： A memory module including memory devices, a spare memory device, a multiplexing unit, and a memory buffer is provided. The multiplexing unit is coupled with each of the memory devices and the spare memory device, while the memory buffer is coupled with the multiplexing unit. The memory buffer includes a serial interface over which commands are received from a memory controller. The memory buffer is configured to process the commands and provide the memory controller access to the memory device through the multiplexing unit in response to the commands. Also, in response to at least one of the commands, the memory buffer is configured to direct the multiplexing unit to couple the spare memory device to the memory buffer in place of one of the memory devices for at least a next access of the memory devices.
摘要翻译：提供了包括存储器件，备用存储器件，复用单元和存储器缓冲器的存储器模块。复用单元与每个存储器件和备用存储器件耦合，而存储器缓冲器与复用单元耦合。存储器缓冲器包括从存储器控制器接收命令的串行接口。存储器缓冲器被配置为处理命令并且通过复用单元响应命令提供存储器控制器对存储器件的访问。此外，响应于至少一个命令，存储器缓冲器被配置为指示复用单元将备用存储器设备代替存储器设备之一耦合到存储器缓冲器，用于存储器设备的至少下一次访问。

5. 发明授权

US08554991B2 High speed interface for dynamic random access memory (DRAM) 有权
标题翻译：用于动态随机存取存储器（DRAM）的高速接口
公开(公告)号：US08554991B2
公开(公告)日：2013-10-08
申请号：US13023991
申请日：2011-02-09
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G06F12/00 , G11C5/08
CPC分类号： G11C7/10
摘要： An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.
摘要翻译：用于动态随机存取存储器（DRAM）的接口包括使用第一附接结构耦合到DRAM芯片的接口元件，第一附接结构的第一部分用于形成宽带宽，低速并行接口，第二所述第一连接结构的部分，与所述DRAM芯片相关联的路由元件和穿通硅通孔（TSV）用于形成窄带宽高速串行接口，所述接口元件被配置为将并行信息转换为串行信息并配置将串行信息转换为并行信息。

6. 发明授权

US08386702B2 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US08386702B2
公开(公告)日：2013-02-26
申请号：US11261270
申请日：2005-10-27
申请人： Larry J. Thayer , Leith L. Johnson
发明人： Larry J. Thayer , Leith L. Johnson
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0866
摘要： In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.
摘要翻译：在一个实施例中，存储器控制系统被提供有存储器控制器，该存储器控制器具有1）用于接收存储器读/写请求的第一接口; 2）从多个存储器模块读取/写入数据的第二接口; 3）包含备用内存位置的内存缓存; 以及4）当接收到存储器读/写请求时，i）当与所述读/写请求相关联的地址驻留在所述存储器高速缓存中时，将所述读/写请求定向到所述存储器高速缓存，以及ii）将所述读/ 当与读/写请求相关联的地址不驻留在存储器高速缓存中时，向第二接口写入请求。

7. 发明申请

US20100275098A1 BIT ERROR RATE REDUCTION BUFFER, METHOD AND APPARATUS 有权
标题翻译：位错误减速缓冲器，方法和装置
公开(公告)号：US20100275098A1
公开(公告)日：2010-10-28
申请号：US12831082
申请日：2010-07-06
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： H03M13/00
CPC分类号： G06F13/4295 , G06F11/1004 , G06F13/1673 , G06F13/1684 , H04B10/40 , H04L1/0001 , H04L1/242 , H04L25/14 , Y02D10/14 , Y02D10/151
摘要： A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.
摘要翻译：所公开的示例性误码率降低缓冲器包括数据恢复电路，其包括差分位对输入和差分位对输出，包括差分位对输入，差分位对输出和故障隔离指示符的CRC电路，以及包括差分位对输入和差分位对输出。数据恢复电路的差分位对输出耦合到CRC电路的差分位对输入，CRC电路的差分位对输出耦合到串行器的差分位对输入，差分位对输入数据恢复电路由第一HSS链路驱动，串行器的不同位对输出驱动第二HSS链路; 以及CRC电路的故障隔离指示灯，以指示当CRC电路检测到故障时的故障。

8. 发明授权

US07539931B2 Storage element for mitigating soft errors in logic 有权
标题翻译：用于缓解逻辑中的软错误的存储元件
公开(公告)号：US07539931B2
公开(公告)日：2009-05-26
申请号：US11102530
申请日：2005-04-08
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G06F11/08
CPC分类号： G11C5/005
摘要： In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit. The delay of the second delayed clock signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
摘要翻译：在优选实施例中，本发明提供了一种减少逻辑中的软错误的方法。在获得两个延迟的时钟信号之后，延迟的时钟信号，时钟信号和来自逻辑电路的输出被施加到三重冗余存储器元件。第一延迟时钟信号的延迟等于或大于在逻辑电路中发生的软错误事件的脉冲宽度。第二延迟时钟信号的延迟等于或大于在逻辑电路中发生的软错误事件的脉冲宽度的一半。

9. 发明申请

US20080077840A1 MEMORY SYSTEM AND METHOD FOR STORING AND CORRECTING DATA 审中-公开
标题翻译：用于存储和校正数据的存储系统和方法
公开(公告)号：US20080077840A1
公开(公告)日：2008-03-27
申请号：US11535776
申请日：2006-09-27
申请人： Mark Shaw , Larry J. Thayer
发明人： Mark Shaw , Larry J. Thayer
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C29/70
摘要： A data memory system is provided which includes a plurality of first data storage devices, at least two second data storage devices, and a third data storage device. The plurality of first data storage devices is configured to store first data. The second data storage devices are configured to store error correction data. Also included in the system is a control circuit configured to generate the error correction data using the first data, correct errors in the first data using the error correction data, and replace one of the plurality of first data storage devices or one of the at least two second data storage devices with the third data storage device.
摘要翻译：提供一种包括多个第一数据存储装置，至少两个第二数据存储装置和第三数据存储装置的数据存储器系统。多个第一数据存储装置被配置为存储第一数据。第二数据存储设备被配置为存储纠错数据。还包括在系统中的控制电路被配置为使用第一数据生成纠错数据，使用纠错数据校正第一数据中的错误，并且替换多个第一数据存储装置中的一个或者至少具有第三数据存储设备的两秒数据存储设备。

10. 发明授权

US08914683B2 Repairing high-speed serial links 有权
标题翻译：修复高速串行链路
公开(公告)号：US08914683B2
公开(公告)日：2014-12-16
申请号：US12241866
申请日：2008-09-30
申请人： Larry J. Thayer
发明人： Larry J. Thayer
IPC分类号： G06F11/00 , G06F11/14 , G06F11/07 , G06F11/20
CPC分类号： G06F11/1443 , G06F11/0745 , G06F11/076 , G06F11/2007
摘要： A method and system for repairing high speed serial links is provided. The system includes a first electronic components, connected to at least a second electronic component via at least one link. At least one of the first or second electronic components has a link controller. The link controller is configured to repair serial links by detecting a link error and mapping out individual lanes of a link where the link error is detected. The link controller resumes operation, i.e., transmission of data and continues to monitor the lanes for errors. If and when additional link errors occur, the link controller identifies the lanes in which the link error occurs and deactivates those lanes. The deactivated lane(s) can not be used in further transmissions which, in turn, reduces the occurrence of intermittent link errors.
摘要翻译：提供了修复高速串行链路的方法和系统。该系统包括经由至少一个链路连接到至少第二电子部件的第一电子部件。第一或第二电子部件中的至少一个具有链路控制器。链路控制器被配置为通过检测链路错误并映射检测到链路错误的链路的各个通道来修复串行链路。链路控制器恢复操作，即传输数据，并继续监视车道的错误。如果发生额外的链路错误，链路控制器会识别发生链路错误的通道，并停用这些通道。停用的通道不能用于进一步的传输，这反过来减少间歇性链路错误的发生。

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