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1. 发明授权

US07725754B1 Dual clock interface for an integrated circuit 有权
标题翻译：集成电路的双时钟接口
公开(公告)号：US07725754B1
公开(公告)日：2010-05-25
申请号：US11500547
申请日：2006-08-08
申请人： Laurent Fabris Stadler
发明人： Laurent Fabris Stadler
IPC分类号： H04L25/00 , H04L25/40 , H04L7/00
CPC分类号： G06F1/08 , H03K19/177
摘要： A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block has a clock divider circuit coupled to receive a user clock signal and a core clock signal for dividing the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal with edges aligned to the core clock signal. The divided clock signal has the frequency of the user clock signal and a phase relationship of the user clock signal. User-side logic is coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal. Core-side logic is coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.
摘要翻译：描述了用于集成电路的双时钟接口。集成电路包括接口电路。接口电路具有硬连线逻辑块。硬连线逻辑块具有时钟分频器电路，其耦合以接收用户时钟信号和核心时钟信号，用于根据用户时钟信号的频率分频核心时钟信号，以提供具有与核心时钟信号对准的边沿的分频时钟信号。分频时钟信号具有用户时钟信号的频率和用户时钟信号的相位关系。用户侧逻辑被耦合以接收分配的时钟信号，以响应于划分的时钟信号来控制信息传递信息。核心侧逻辑被耦合以接收核心时钟信号，以响应于核心时钟信号受控地传递信息。

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