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1. 发明授权

US08044829B2 Multi-mode encoding for data compression 有权
标题翻译：用于数据压缩的多模式编码
公开(公告)号：US08044829B2
公开(公告)日：2011-10-25
申请号：US12713692
申请日：2010-02-26
申请人： Liang-Chieh Chen , Xueshi Yang
发明人： Liang-Chieh Chen , Xueshi Yang
IPC分类号： H03M7/34 , H03M7/38
CPC分类号： H03M7/3086 , H03M7/48
摘要： The present disclosure includes apparatus, systems and techniques relating to lossless data compression. In some implementations, an apparatus includes a memory module to store data. The memory module includes a first buffer portion to store encoded symbols of the data, and a second buffer portion to store symbols of the data to be encoded. The apparatus includes an encoder to compare the symbols stored in the second buffer portion with the encoded symbols stored in the first buffer portion and to compress the data. The encoder can operate in a first encoding mode to encode the symbols in the second buffer portion with corresponding codewords until detecting a repeated pattern of symbols in the second buffer portion that matches the encoded symbols in the first buffer portion. The encoder can operate in a second encoding mode responsive to detecting the repeated pattern.
摘要翻译：本公开包括与无损数据压缩相关的装置，系统和技术。在一些实现中，装置包括用于存储数据的存储器模块。存储器模块包括用于存储数据的编码符号的第一缓冲器部分和用于存储要被编码的数据的符号的第二缓冲器部分。该装置包括编码器，用于将存储在第二缓冲器部分中的符号与存储在第一缓冲器部分中的编码符号进行比较并压缩数据。编码器可以以第一编码模式操作，以用相应的码字对第二缓冲器部分中的符号进行编码，直到检测到与第一缓冲器部分中的编码符号匹配的第二缓冲器部分中的重复符号模式。响应于检测到重复模式，编码器可以以第二编码模式操作。

2. 发明申请

US20100225506A1 Multi-Mode Encoding for Data Compression 有权
标题翻译：用于数据压缩的多模式编码
公开(公告)号：US20100225506A1
公开(公告)日：2010-09-09
申请号：US12713692
申请日：2010-02-26
申请人： Liang-Chieh Chen , Xueshi Yang
发明人： Liang-Chieh Chen , Xueshi Yang
IPC分类号： H03M7/34
CPC分类号： H03M7/3086 , H03M7/48
摘要： The present disclosure includes apparatus, systems and techniques relating to lossless data compression. In some implementations, an apparatus includes a memory module to store data. The memory module includes a first buffer portion to store encoded symbols of the data, and a second buffer portion to store symbols of the data to be encoded. The apparatus includes an encoder to compare the symbols stored in the second buffer portion with the encoded symbols stored in the first buffer portion and to compress the data. The encoder can operate in a first encoding mode to encode the symbols in the second buffer portion with corresponding codewords until detecting a repeated pattern of symbols in the second buffer portion that matches the encoded symbols in the first buffer portion. The encoder can operate in a second encoding mode responsive to detecting the repeated pattern.
摘要翻译：本公开包括与无损数据压缩相关的装置，系统和技术。在一些实现中，装置包括用于存储数据的存储器模块。存储器模块包括用于存储数据的编码符号的第一缓冲器部分和用于存储要被编码的数据的符号的第二缓冲器部分。该装置包括编码器，用于将存储在第二缓冲器部分中的符号与存储在第一缓冲器部分中的编码符号进行比较并压缩数据。编码器可以以第一编码模式操作，以用相应的码字对第二缓冲器部分中的符号进行编码，直到检测到与第一缓冲器部分中的编码符号匹配的第二缓冲器部分中的重复符号模式。响应于检测到重复模式，编码器可以以第二编码模式操作。

3. 发明授权

US08223545B1 Systems and methods for data page management of NAND flash memory arrangements 有权
标题翻译： NAND闪存安排的数据页面管理系统和方法
公开(公告)号：US08223545B1
公开(公告)日：2012-07-17
申请号：US12611837
申请日：2009-11-03
申请人： Liang-Chieh Chen , Xueshi Yang
发明人： Liang-Chieh Chen , Xueshi Yang
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C2211/5641
摘要： Embodiments of the present disclosure provide methods and apparatus for providing a NAND flash memory arrangement that comprises a source select line (SSL), a drain select line (DSL) and a plurality of NAND memory cells arranged to provide a plurality of data pages. The method further includes defining a first set of data pages in close proximity to the SSL, defining a second set of data pages in close proximity to the DSL, and differentiating the first set of data pages and the second set of data pages from at least the remaining data pages.
摘要翻译：本公开的实施例提供了用于提供NAND闪速存储器装置的方法和装置，其包括源选择线（SSL），漏极选择线（DSL）以及布置成提供多个数据页的多个NAND存储器单元。该方法还包括定义靠近SSL的第一组数据页面，定义靠近DSL的第二组数据页面，并且至少将第一组数据页面和第二组数据页面区分开剩余的数据页。

4. 发明授权

US09048879B1 Error correction system using an iterative product code 有权
标题翻译：纠错系统使用迭代产品代码
公开(公告)号：US09048879B1
公开(公告)日：2015-06-02
申请号：US13586710
申请日：2012-08-15
申请人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
发明人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
IPC分类号： H03M13/29 , H04L1/00
CPC分类号： H03M13/2945 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/23 , H03M13/2909 , H03M13/2957 , H03M13/3746 , H04L1/0065
摘要： An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
摘要翻译：纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。在一些实施例中，在传输侧，在输入节点处接收的输入信号基于交织的代码进行编码，该代码编码输入数据的交错版本以产生第一组码字。第一组码字的至少一部分优选地被划分为多个符号，这些符号基于嵌入的奇偶校验码被编码以提供编码数据。类似地，在一些实施例中，在接收侧，检测所接收的数据以产生检测到的信息和软输出。检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

5. 发明授权

US09015562B1 Systems and methods for multistage error correction 有权
标题翻译：用于多级纠错的系统和方法
公开(公告)号：US09015562B1
公开(公告)日：2015-04-21
申请号：US12543006
申请日：2009-08-18
申请人： Shumei Song , Xueshi Yang
发明人： Shumei Song , Xueshi Yang
IPC分类号： G11B20/18 , G11B19/02
CPC分类号： G11B19/025 , G11B20/1833 , G11B2020/1859
摘要： In one embodiment, the present invention includes an error correction method. The error correction method comprises receiving a digital signal and processing the digital signal to perform a first error correction. The first error correction includes a first correction for data insertions or deletions and a first correction of data errors to generate a reference signal. The reference signal corresponds to the digital signal having been corrected to a first correction accuracy. The digital signal and the reference signal may be processed to perform a second correction for data insertions or deletions to generate a synchronized signal. The second correction of the digital signal is based on the reference signal, and the correction accuracy of the second correction is more accurate than the first correction accuracy.
摘要翻译：在一个实施例中，本发明包括纠错方法。误差校正方法包括接收数字信号并处理数字信号以执行第一纠错。第一纠错包括用于数据插入或删除的第一校正以及数据错误的第一校正以产生参考信号。参考信号对应于已被校正为第一校正精度的数字信号。数字信号和参考信号可以被处理以执行用于数据插入或删除的第二校正以产生同步信号。数字信号的第二校正基于参考信号，并且第二校正的校正精度比第一校正精度更准确。

6. 发明授权

US08635508B2 Systems and methods for performing concatenated error correction 有权
标题翻译：用于执行连接纠错的系统和方法
公开(公告)号：US08635508B2
公开(公告)日：2014-01-21
申请号：US13604391
申请日：2012-09-05
申请人： Xueshi Yang , Zining Wu , Seo-How Low
发明人： Xueshi Yang , Zining Wu , Seo-How Low
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , G06F11/1072 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
摘要翻译：提供了一种用于执行串联纠错的系统和方法。在一个实施方式中，用于编码数据的装置包括外编码器，用于产生与所接收的输入数据相对应的代码字，以及奇偶校验电路来计算数据的逻辑单元的奇偶校验，数据的逻辑单元从代码字获得并具有第一个逻辑单元。该装置还包括内编码器，用于基于与第一逻辑单元相对应的第一奇偶校验位产生第一逻辑单元的纠错位，并将误差校正位插入第一逻辑单元。

7. 发明授权

US08611151B1 Flash memory read performance 有权
公开(公告)号：US08611151B1
公开(公告)日：2013-12-17
申请号：US13268183
申请日：2011-10-07
申请人： Xueshi Yang
发明人： Xueshi Yang
IPC分类号： G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C16/0483 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/0408 , G11C16/06 , G11C16/26 , G11C16/28 , G11C16/344 , G11C2211/5634 , G11C2216/16
摘要： This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for reducing the amount of hardware and processing resources of a flash controller to read an amount of data. These techniques effectively increase the speed at which flash memory can be read by the flash controller without modifying conventional flash memories.

8. 发明授权

US08437193B1 Flash memory data recovery 有权
标题翻译：闪存数据恢复
公开(公告)号：US08437193B1
公开(公告)日：2013-05-07
申请号：US12820266
申请日：2010-06-22
申请人： Xueshi Yang
发明人： Xueshi Yang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5621 , G11C16/04 , G11C16/349
摘要： An apparatus and method for selectively controlling application of a data recovery bias voltage are described. One example apparatus includes replenish logic configured to selectively control application of a data recovery bias voltage to a control gate associated with a cell in a flash memory apparatus. The replenish logic may be configured to select the data recovery bias voltage to replenish charge lost from a floating gate in the flash memory apparatus. The replenish logic may also be configured to control application of the data recovery bias voltage for a period of time sufficient to charge a threshold voltage (Vt) in the cell. In one embodiment, the data recovery bias voltage is based on a program voltage employed to program a value into the cell.
摘要翻译：描述了用于选择性地控制数据恢复偏置电压的应用的装置和方法。一个示例性设备包括补充逻辑，其被配置为选择性地控制数据恢复偏置电压到与闪存设备中的单元相关联的控制门的应用。补充逻辑可以被配置为选择数据恢复偏置电压以补充从闪存设备中的浮动栅极丢失的电荷。补充逻辑还可以被配置为控制数据恢复偏置电压的施加足以对单元中的阈值电压（Vt）充电的时间段。在一个实施例中，数据恢复偏置电压基于用于将值编程到单元中的编程电压。

9. 发明授权

US08416623B2 Reference voltage optimization for flash memory 有权
标题翻译： Flash存储器参考电压优化
公开(公告)号：US08416623B2
公开(公告)日：2013-04-09
申请号：US13447789
申请日：2012-04-16
申请人： Xueshi Yang
发明人： Xueshi Yang
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/30 , H01L27/115
摘要： A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.
摘要翻译：系统包括电压发生器和参考电压设定模块。电压发生器被配置为产生要施加到存储器单元的K电压。 K电压用于确定用于读取存储器单元的参考电压，其中K是大于1的整数。参考电压设置模块被配置为选择性地将参考电压设置为K个电压中的两个相邻电压之间的值或K个电压中的两个相邻的电压之一。

10. 发明授权

US08406048B2 Accessing memory using fractional reference voltages 有权
$Accessing memory using fractional reference voltages$
标题翻译：使用分数参考电压访问存储器
公开(公告)号：US08406048B2
公开(公告)日：2013-03-26
申请号：US12535987
申请日：2009-08-05
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/10 , G11C16/28 , G11C2211/5634
摘要： Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.
摘要翻译：描述了使用分数参考电压访问存储器的设备，系统，方法和其他实施例。在一个实施例中，一种装置包括比较逻辑。比较逻辑将存储器单元的阈值电压与至少一对分数参考电压进行比较以产生比较结果。该装置包括至少部分地基于比较结果来确定存储器单元的位值的读取逻辑。

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