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1. 发明申请

US20190109606A1 METHOD FOR REDUCING DIRECT DIGITAL SYNTHESIZER (DDS) AND MIXER SPURIOUS 审中-公开
公开(公告)号：US20190109606A1
公开(公告)日：2019-04-11
申请号：US16154375
申请日：2018-10-08
申请人： Lockheed Martin Corporation
发明人： Peter L. Delos , Douglas A. Leonard, JR.
IPC分类号： H04B1/04
摘要： A method of producing a low spurious output signal in a frequency generator circuit comprises, in a direct digital synthesizer (DDS), generating a signal at a first frequency; mixing the signal to produce a signal at a second frequency in an operating band of interest higher than the first frequency; determining spurious signals in the second frequency signal due to non-linearity in a digital to analog converter (DAC) of the DDS; generating at least one amplitude and frequency vector containing information relating to an amplitude value and frequency value representative of one of the determined spurious energy signals; generating a pre-distortion signal based on the at least one amplitude and frequency vector; and combining the pre-distortion signal with the signal generated by the DDS to produce a corrected output signal, wherein the pre-distortion signal is phase offset from a corresponding determined spurious signal to cancel the corresponding determined spurious signal.

2. 发明授权

US09112483B1 Offset regenerative frequency divider 有权
标题翻译：偏移再生分频器
公开(公告)号：US09112483B1
公开(公告)日：2015-08-18
申请号：US14034087
申请日：2013-09-23
申请人： Lockheed Martin Corporation
发明人： Peter L. Delos , Francis X. McGroary , Edward F. Gross
IPC分类号： H03B19/00 , H03K3/013
CPC分类号： H03B19/12 , H03K3/013
摘要： A frequency synthesizing circuit comprising a first mixer configured to receive a first input signal, a first filter configured to receive an output of the first mixer and to remove undesired frequency signals from the output signal of the first mixer, and a feedback loop configured to provide an output of the first filter to an input of the first mixer. The feedback loop comprises a second mixer arranged within the feedback loop configured to receive the output of the first filter and to mix the output of the first filter with a second input signal.
摘要翻译：一种频率合成电路，包括被配置为接收第一输入信号的第一混频器，被配置为接收第一混频器的输出并从第一混频器的输出信号中去除不需要的频率信号的第一滤波器，以及被配置为提供第一滤波器的输出到第一混频器的输入端。反馈回路包括布置在反馈回路内的第二混合器，其被配置为接收第一滤波器的输出并将第一滤波器的输出与第二输入信号混合。

3. 发明授权

US10097219B1 Method and system for reducing direct digital synthesizer (DDS) and mixer spurios 有权
公开(公告)号：US10097219B1
公开(公告)日：2018-10-09
申请号：US14486355
申请日：2014-09-15
申请人： Lockheed Martin Corporation
发明人： Peter L. Delos , Douglas A. Leonard, Jr.
IPC分类号： G06F13/38 , H04B1/04
摘要： A waveform generator circuit provides low spurious output signal and includes a primary DDS for generating a RF signal at a first frequency. A DAC receives an output signal from the primary DDS and converts the digital DDS output to an analog output. A spectrum analyzer identifies spurious signals in the DAC output determining the amplitude and frequency characteristics of the spurious signals. The waveform generator includes at least one cancellation DDS configured to generate a pre-distortion signal corresponding to frequencies where spurious signals are expected due to non-linearities in the DAC circuitry. The pre-distortion signals are phase offset from the determined spurious signals to cancel the spurious signals. The pre-distortion signals are combined with the output of the primary DDS. The combined signal contains the primary DDS output signal and pre-distortion signals to produce an analog output signal which cancels out the expected spurious signals.

4. 发明授权

US09531356B1 Integrated circuit with low phase noise clock distribution network 有权
标题翻译：具有低相位噪声时钟分配网络的集成电路
公开(公告)号：US09531356B1
公开(公告)日：2016-12-27
申请号：US14512917
申请日：2014-10-13
申请人： Lockheed Martin Corporation
发明人： Peter L. Delos , Brandon R. Davis , Steven M. Fireman
IPC分类号： H03K21/00 , H03K5/00 , H03K5/13
CPC分类号： H03K5/00006 , H03K5/13
摘要： An integrated circuit includes a clock distribution circuit and a logic block circuit. The clock distribution circuit is segregated from the logic block circuit to restrict contributors to phase noise to the clock distribution section of the circuit. The clock distribution circuit includes a front-end amplifier which buffers a clock input signal to a differential clock signal. The front-end amplifier is configured with as few components as possible and the components are selected for high current density and sized to minimize contributions to phase noise in the clock distribution circuit. The clock distribution circuit further includes an output latch circuit that receives the output signal of the logic block circuit and the low phase noise differential clock input signal from the front-end amplifier circuit. The output latch circuit re-clocks the final output of the integrated circuit. The output is representative of the output values determined by the logic block circuit.
摘要翻译：集成电路包括时钟分配电路和逻辑块电路。时钟分配电路与逻辑块电路分离，以将相位噪声的贡献者限制到电路的时钟分配部分。时钟分配电路包括将时钟输入信号缓冲到差分时钟信号的前端放大器。前端放大器配置有尽可能少的组件，并且选择组件用于高电流密度和大小以最小化对时钟分配电路中的相位噪声的贡献。时钟分配电路还包括输出锁存电路，其接收来自前端放大器电路的逻辑块电路的输出信号和低相位噪声差分时钟输入信号。输出锁存电路重新计时集成电路的最终输出。输出代表由逻辑块电路确定的输出值。

5. 发明授权

US09531324B1 Frequency synthesizer system and method 有权
标题翻译：频率合成器系统及方法
公开(公告)号：US09531324B1
公开(公告)日：2016-12-27
申请号：US14788958
申请日：2015-07-01
申请人： Lockheed Martin Corporation
发明人： Peter L. Delos , Francis X. McGroary , Edward F. Gross
IPC分类号： H03B21/00 , H03B19/12 , H03K3/013
CPC分类号： H03B19/12 , H03K3/013
摘要： A frequency synthesizing circuit comprising a first mixer configured to receive a first input signal at a first input thereof, a first filter configured to receive an output signal of the first mixer and remove undesired signal frequencies from the output signal of the first mixer, and a feedback loop. The feedback loop includes a second mixer having a first input connected to the output of the first filter and a second input for receiving a second input signal. The second mixer is configured to mix a signal received at the first input with the second input signal. The feedback loop further includes a third mixer having a first input connected to an output of the second mixer and a second input for receiving a third input signal. The third mixer is configured to mix a signal received at the first input with the third input signal.
摘要翻译：一种频率合成电路，包括：第一混频器，被配置为在其第一输入处接收第一输入信号;第一滤波器，被配置为接收第一混频器的输出信号，并从第一混频器的输出信号中去除不需要的信号频率，反馈回路。反馈环路包括具有连接到第一滤波器的输出端的第一输入端和用于接收第二输入信号的第二输入端的第二混频器。第二混频器被配置为将在第一输入处接收到的信号与第二输入信号进行混合。反馈环路还包括具有连接到第二混频器的输出端的第一输入端和用于接收第三输入信号的第二输入端的第三混频器。第三混频器被配置为将在第一输入处接收的信号与第三输入信号混合。

6. 发明授权

US09473158B1 Radio frequency receiver with overlapped analog to digital converter (ADC) architecture 有权
标题翻译：具有重叠模数转换器（ADC）架构的射频接收机
公开(公告)号：US09473158B1
公开(公告)日：2016-10-18
申请号：US14870250
申请日：2015-09-30
申请人： Lockheed Martin Corporation
发明人： Peter L. Delos
IPC分类号： H03M1/12 , H04B1/06
CPC分类号： H04B1/06 , H03M1/121
摘要： A radio frequency receiver includes a first and second analog to digital converter (ADC) connected in parallel. Each ADC is coupled to a corresponding mixer that receives a local oscillator (LO) frequency signal and an analog input signal. Each LO down-converts the analog input signal to a band of frequencies falling within the band of operation of the LO's corresponding ADC. The frequency is selected such that each LO down-converts the input signal such that a portion of the operating band of each LO overlaps. For frequencies falling within the overlapped region, each ADC samples the overlapped frequency band and the corresponding outputs of the parallel ADCs are coherently summed to provide an output having up to about 3 dB improvement in SNR. For sampled frequencies outside the overlapped frequency range, a single corresponding ADC samples the signal which is down coverted and equalized to generate a direct output to expand the instantaneous bandwidth of the receiver.
摘要翻译：射频接收机包括并联连接的第一和第二模数转换器（ADC）。每个ADC耦合到相应的混频器，其接收本地振荡器（LO）频率信号和模拟输入信号。每个LO将模拟输入信号降频转换为落在LO对应的ADC的工作频带内的频带。选择频率使得每个LO对输入信号进行下变频，使得每个LO的工作频带的一部分重叠。对于落在重叠区域内的频率，每个ADC对重叠的频带进行采样，并行并行ADC的相应输出被相加相加，以提供高达SNR约3 dB的输出。对于重叠频率范围之外的采样频率，单个对应的ADC对被覆盖和均衡的信号进行采样，以产生直接输出以扩展接收机的瞬时带宽。

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