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1. 发明授权

US4645881A DC level trip detector 失效
标题翻译：直流电平跳闸检测器
公开(公告)号：US4645881A
公开(公告)日：1987-02-24
申请号：US662860
申请日：1984-10-19
申请人： Loic LeToumelin , Franck Tollon , Yves Leduc
发明人： Loic LeToumelin , Franck Tollon , Yves Leduc
IPC分类号： H04L27/00 , H04M3/02 , H04M3/06 , H04M19/02 , H04Q3/00
CPC分类号： H04M19/026
摘要： The method includes generating a binary signal (S4A to S4D) which is time modulated. To do this, an alternating signal (S1) is compared with a known cyclical signal (S5) and a threshold signal. There is measured the durations between the transitions of the modulated signal by means of a high speed clock and by means of counting in the positive and negative directions of the clock pulses for one or more periods of the signal under examination. If, after counting, a residual value is found, one generates a binary signal representing the transition.
摘要翻译：该方法包括生成被时间调制的二进制信号（S4A至S4D）。为此，将交替信号（S1）与已知的周期信号（S5）和阈值信号进行比较。通过高速时钟测量调制信号的转换之间的持续时间，并通过对正在检测的信号的一个或多个周期的时钟脉冲的正和负方向进行计数。如果在计数之后找到剩余值，则产生表示转换的二进制信号。

2. 发明申请

US20050077945A1 Low power, up full swing voltage CMOS bus receiver 有权
标题翻译：低功耗，全高电压CMOS总线接收器
公开(公告)号：US20050077945A1
公开(公告)日：2005-04-14
申请号：US10860522
申请日：2004-06-03
申请人： Nathalie Messina , Yves Leduc
发明人： Nathalie Messina , Yves Leduc
IPC分类号： G06F13/40 , H03B1/00 , H03K3/356 , H03L5/00
CPC分类号： H03K3/356147 , G06F13/4072 , H03K3/356113 , Y02D10/14 , Y02D10/151
摘要： A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors. A fifth MOS transistor is provided, connected in series by a source and drain with a diode between the first side of the power supply and the input node, a gate of the fourth MOS transistor being connected to the common connection node of the fifth MOS transistor and the diode. An inverter has an input connected to the output node and an output connected to a gate of the fifth MOS transistor.
摘要翻译：一种CMOS总线接收器，用于将输入节点处的降低的电压摆幅输入信号转换为输出节点处的较高电压摆幅输出信号。接收器包括通过其源极和漏极在电源的第一侧和第二侧串联连接的第一和第二MOS晶体管，第一MOS晶体管的栅极连接到输入节点，公共连接节点第一和第二MOS晶体管连接到输出节点。还提供了通过其电源的第一侧和输入节点之间的源极和漏极串联连接的第三和第四MOS晶体管，第三MOS晶体管的栅极连接到输出节点，并且栅极第二MOS晶体管连接到第三和第四MOS晶体管的公共连接节点。提供第五MOS晶体管，其通过源极和漏极串联连接在电源的第一侧和输入节点之间的二极管，第四MOS晶体管的栅极连接到第五MOS晶体管的公共连接节点和二极管。逆变器具有连接到输出节点的输入端和连接到第五MOS晶体管的栅极的输出端。

3. 发明授权

US06960946B2 Low power, up full swing voltage CMOS bus receiver 有权
公开(公告)号：US06960946B2
公开(公告)日：2005-11-01
申请号：US10860522
申请日：2004-06-03
申请人： Nathalie Messina , Yves Leduc
发明人： Nathalie Messina , Yves Leduc
IPC分类号： G06F13/40 , H03B1/00 , H03K3/356 , H03L5/00
CPC分类号： H03K3/356147 , G06F13/4072 , H03K3/356113 , Y02D10/14 , Y02D10/151
摘要： A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors. A fifth MOS transistor is provided, connected in series by a source and drain with a diode between the first side of the power supply and the input node, a gate of the fourth MOS transistor being connected to the common connection node of the fifth MOS transistor and the diode. An inverter has an input connected to the output node and an output connected to a gate of the fifth MOS transistor.

4. 发明授权

US07872841B2 In package ESD protections of IC using a thin film polymer 有权
标题翻译：使用薄膜聚合物封装ESD保护IC
公开(公告)号：US07872841B2
公开(公告)日：2011-01-18
申请号：US12049726
申请日：2008-03-17
申请人： Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
发明人： Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
IPC分类号： H02H9/00
CPC分类号： H01L23/62 , H01L23/60 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2924/00014 , H01L2924/13034 , H01L2924/15311 , H05K1/0259 , H05K2201/0738 , Y10T29/49105 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
摘要翻译：一种封装半导体器件（200），其具有夹在绝缘体（221）中的基板（220），由预定电压从绝缘体切换到导体模式的非线性材料制成的平板状筛件（240）。两个构件表面都没有压痕; 所述构件穿过通孔，所述通孔被分组成第一组（241）和第二组（242）。一个构件表面上的金属迹线（251）跨过第一组通孔（241）定位; 每个迹线连接到基板顶部上的端子，并且通过孔连接到基板底部上的端子。类似于相对构件表面上的金属迹线（252）和第二组通孔（242）。轨迹（252）与轨迹（252）的一部分重叠以形成用于导电开关的位置，从而产生局部超低电阻旁路到地以释放过应力事件。

5. 发明授权

US5021787A Digital-analog converter for conversion of law A- encoded digital signals into analog signals 失效
标题翻译：数字模拟转换器，用于将A编码的数字信号转换为模拟信号
公开(公告)号：US5021787A
公开(公告)日：1991-06-04
申请号：US518375
申请日：1990-05-03
申请人： Yves Leduc
发明人： Yves Leduc
IPC分类号： H03M1/66 , H03M1/68 , H03M1/80
CPC分类号： H03M1/664 , H03M1/68 , H03M1/804
摘要： Digital-analog converter intended to convert into analog signals digital signals formed of sign bits, of step bits and of segment bits, particularly signals coded by data compression according to law A, the said converter comprising a sign generator (4), intended to receive the sign bit of the said digital signal, a step generator (7), connected to the output of the sign generator and intended to receive the step bits of the said digital signal and to a segment generator (8) connected to the step generator and intended to receive the segment bits of the said digital signal, characterized in that the segment generator (8) is connected to the sign generator by means of the step generator (7) only.
摘要翻译：数字 - 模拟转换器旨在转换成模拟信号，由符号位，步进位和分段位组成的数字信号，特别是依据A的数据压缩编码的信号，所述转换器包括用于接收的符号发生器（4）所述数字信号的符号位，步进发生器（7），连接到所述符号发生器的输出并且用于接收所述数字信号的步进位，并连接到与步进发生器连接的段发生器（8），以及旨在接收所述数字信号的分段比特，其特征在于，段发生器（8）仅通过步进发生器（7）连接到符号发生器。

6. 发明申请

US20110075306A1 LOCAL INTEGRATION OF NON-LINEAR SHEET I INTEGRATED CIRCUIT PACKAGES FOR ESD/EOS PROTECTION 审中-公开
标题翻译：非线性片I I集成电路组件ESD / EOS保护的本地集成
公开(公告)号：US20110075306A1
公开(公告)日：2011-03-31
申请号：US12963704
申请日：2010-12-09
申请人： Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
发明人： Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
IPC分类号： H02H9/04
CPC分类号： H01L23/62 , H01L23/60 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2924/00014 , H01L2924/13034 , H01L2924/15311 , H05K1/0259 , H05K2201/0738 , Y10T29/49105 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
摘要翻译：一种封装半导体器件（200），其具有夹在绝缘体（221）中的基板（220），由预定电压从绝缘体切换到导体模式的非线性材料制成的平板状筛件（240）。两个构件表面都没有压痕; 所述构件穿过通孔，所述通孔被分组成第一组（241）和第二组（242）。一个构件表面上的金属迹线（251）跨过第一组通孔（241）定位; 每个迹线连接到基板顶部上的端子，并且通过孔连接到基板底部上的端子。类似于相对构件表面上的金属迹线（252）和第二组通孔（242）。轨迹（252）与轨迹（252）的一部分重叠以形成用于导电开关的位置，从而产生局部超低电阻旁路到地以释放过应力事件。

7. 发明授权

US06400231B1 Numerically controlled variable oscillator 有权
标题翻译：数控可变振荡器
公开(公告)号：US06400231B1
公开(公告)日：2002-06-04
申请号：US09642481
申请日：2000-08-18
申请人： Yves Leduc , Pascal Guignon , Pierre Carbou
发明人： Yves Leduc , Pascal Guignon , Pierre Carbou
IPC分类号： H03B500
CPC分类号： H03K3/0307 , H03B5/366 , H03J2200/10
摘要： An oscillator includes a resonator, such as a crystal (12) coupled to first and second capacitor banks (14). The first and second capacitor banks (14) each comprise a plurality of capacitors (16) coupled to the resonator (12) through respective switching devices (18) that may be selectively enabled. The switches (18) are selectively enabled to couple a desired set of said capacitors (16) to said resonator (12). At least one of the switches (18sd) is controlled with a clock signal having a programmable duty cycle from a sigma-delta modulator (20) to enable at least one of said capacitors (16sd) during a first phase of the clock signal and disable that capacitor (16sd) during a second phase of the clock signal.
摘要翻译：振荡器包括谐振器，例如耦合到第一和第二电容器组（14）的晶体（12）。第一和第二电容器组（14）各自包括通过可以选择性地使能的各个开关装置（18）耦合到谐振器（12）的多个电容器（16）。选择性地使开关（18）能够将期望的所述电容器组（16）耦合到所述谐振器（12）。至少一个开关（18sd）由具有来自Σ-Δ调制器（20）的可编程占空比的时钟信号控制，以在时钟信号的第一阶段期间使能至少一个所述电容器（16sd），并且使能该电容器（16sd）在时钟信号的第二阶段期间。

8. 发明申请

US20080278873A1 IN PACKAGE ESD PROTECTIONS OF IC USING A THIN FILM POLYMER 有权
标题翻译：使用薄膜聚合物的IC封装ESD保护
公开(公告)号：US20080278873A1
公开(公告)日：2008-11-13
申请号：US12049726
申请日：2008-03-17
申请人： Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
发明人： Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
IPC分类号： H02H9/04 , H01H11/00
CPC分类号： H01L23/62 , H01L23/60 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2924/00014 , H01L2924/13034 , H01L2924/15311 , H05K1/0259 , H05K2201/0738 , Y10T29/49105 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
摘要翻译：一种封装半导体器件（200），其具有夹在绝缘体（221）中的基板（220），由预定电压从绝缘体切换到导体模式的非线性材料制成的平板状筛构件（240）。两个构件表面都没有压痕; 所述构件穿过通孔，所述通孔被分组成第一组（241）和第二组（242）。一个构件表面上的金属迹线（251）跨过第一组通孔（241）定位; 每个迹线连接到基板顶部上的端子，并且通过孔连接到基板底部上的端子。类似于相对构件表面上的金属迹线（252）和第二组通孔（242）。轨迹（252）与轨迹（252）的一部分重叠以形成用于导电开关的位置，从而产生局部超低电阻旁路到地以释放过应力事件。

9. 发明授权

US5841386A Simple high resolution monolithic DAC for the tuning of an external VCXO (voltage controlled quartz oscillator) 失效
标题翻译：用于调谐外部VCXO（压控石英振荡器）的简单高分辨率单片DAC
公开(公告)号：US5841386A
公开(公告)日：1998-11-24
申请号：US786524
申请日：1997-01-21
申请人： Yves Leduc
发明人： Yves Leduc
IPC分类号： H03M3/02 , H03M7/32 , H03M7/36
CPC分类号： H03M3/504
摘要： This invention relates to a high-resolution digital/analogue converter intended in particular for the tuning of a voltage-controlled quartz oscillator. This converter comprises a first second-order Sigma-Delta modulator (1) to the output of which is connected the input of a second Sigma-Delta modulator (9) producing a single bit at its output and a digital/analogue conversion circuit (13). The circuit of the converter furthermore comprises means for filtering the high-frequency components of the signal undergoing processing so as to obtain a quasi-stable D.C. voltage source with a high resolution. This invention is applicable to any voltage-controlled system having large inertia, and in particular, voltage-controlled quartz oscillators and transducers.
摘要翻译：本发明涉及特别用于调谐压控石英振荡器的高分辨率数字/模拟转换器。该转换器包括第一二阶Σ-Δ调制器（1），其输出端连接第二Σ-Δ调制器（9）的输出端，在其输出端产生单个位，以及数字/模拟转换电路（13 ）。转换器的电路还包括用于对正在进行处理的信号的高频分量进行滤波以获得具有高分辨率的准稳态直流电压源的装置。本发明适用于任何具有大惯性的电压控制系统，特别是压控石英振荡器和换能器。

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