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    • 1. 发明申请
    • Handling interrupts in data processing
    • 处理数据处理中断
    • US20090177830A1
    • 2009-07-09
    • US12379970
    • 2009-03-05
    • Luc OrionDavid Hennah MansellMichael Robert Nonweiler
    • Luc OrionDavid Hennah MansellMichael Robert Nonweiler
    • G06F13/24
    • G06F9/4812G06F11/3636G06F11/3656G06F11/3664
    • A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.
    • 一种处理数据的方法,包括:使用可执行多个功能的处理器处理功能,所述处理器具有使能的中断; 在处理器处接收中断; 暂停处理功能; 访问至少一个控制参数,所述至少一个控制参数指示是否应该从其被中断的点恢复该功能的处理,或者该中断之后应该重复该功能; 在完成功能开始的中断继续处理之后,或者根据控制参数中断处理中断点。 作为应用程序,线程,系统软件程序或由软件定义的多个处理步骤的功能。
    • 5. 发明授权
    • Apparatus and method for controlling access to a memory
    • US07171539B2
    • 2007-01-30
    • US10713454
    • 2003-11-17
    • David Hennah MansellMichael Robert NonweilerPeter Guy Middleton
    • David Hennah MansellMichael Robert NonweilerPeter Guy Middleton
    • G06F12/14
    • G06F12/1491G06F12/1036G06F12/1063G06F12/109G06F12/145
    • The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required. At least one memory management unit is provided which is operable, upon receipt of the memory access request from the processor, to perform conversion of a virtual address specified by the memory access request to a physical address. A first set of tables is provided, each table in the first set containing a number of first descriptors, each first descriptor containing at least a virtual address portion and a corresponding intermediate address portion, and a second set of tables is also provided, with each table in the second set containing a number of second descriptors, each second descriptor containing at least an intermediate address portion and a corresponding physical address portion. The second set of tables are managed by the processor when operating in a privileged mode which is not a non-secure mode, and hence remains secure. The at least one memory management unit is then operable to cause predetermined tables in the first and second set to be referenced to enable the conversion of the virtual address specified by the memory access request to a physical address.
    • 6. 发明授权
    • Diagnostic data capture control for multi-domain processors
    • 多域处理器的诊断数据捕获控制
    • US08082589B2
    • 2011-12-20
    • US10714178
    • 2003-11-17
    • Luc OrionDavid Hennah Mansell
    • Luc OrionDavid Hennah Mansell
    • H04N7/16
    • G06F21/71G06F2221/2105
    • There is provided a processor operable in a first domain and a second domain, the processor comprising: monitoring logic operable to monitor the processor and capture diagnostic data; a storage element operable to contain at least one control parameter; control logic operable to control the monitoring logic in dependence on the at least one control parameter and the domain in which the processor is operating, to suppress capturing of diagnostic data relating to predetermined activities of the processor in the first domain. In some embodiments the first domain is a secure domain and the second domain is a non-secure domain, the monitoring function being debug or trace.
    • 提供了可在第一域和第二域中操作的处理器,所述处理器包括:监视逻辑,可操作以监视处理器并捕获诊断数据; 存储元件,其可操作以包含至少一个控制参数; 控制逻辑可操作以根据所述至少一个控制参数和所述处理器在其中操作的所述域来控制所述监视逻辑,以抑制与所述第一域中的所述处理器的预定活动有关的诊断数据的捕获。 在一些实施例中,第一域是安全域,而第二域是非安全域,监视功能是调试或跟踪。