专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10049764B2 Control method for memory device and memory controller 有权
公开(公告)号：US10049764B2
公开(公告)日：2018-08-14
申请号：US15614654
申请日：2017-06-06
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Yu-Ming Huang , Hsiang-Pang Li , Kun-Cheng Hsu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C16/06 , G11C29/44 , G06F11/27 , G11C29/10 , G11C29/12
CPC分类号： G11C29/44 , G06F11/1012 , G06F11/27 , G11C8/14 , G11C29/10 , G11C2029/1202 , H03M13/13
摘要： A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell.

2. 发明授权

US09652179B2 Memory system and a data managing method thereof 有权
公开(公告)号：US09652179B2
公开(公告)日：2017-05-16
申请号：US14811970
申请日：2015-07-29
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Hung-Sheng Chang , Hsiang-Pang Li , Chun-Ta Lin , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06
CPC分类号： G06F3/0673 , G06F3/0608 , G06F3/061 , G06F3/064 , G06F3/0641
摘要： A memory system is provided. The memory system includes a memory controller and a first memory block. The first memory block is configured to store a first data from a top of the first memory block in a top-down fashion. The first memory block is configured to store a first metadata corresponding to the first data from a bottom of the first memory block in a bottom-up fashion. The first data forms a first data area. The first metadata forms a first metadata area. And a first continuous space is formed between a bottom of the first data area and a top of the first metadata area.

3. 发明授权

US09627072B2 Variant operation sequences for multibit memory 有权
公开(公告)号：US09627072B2
公开(公告)日：2017-04-18
申请号：US14857598
申请日：2015-09-17
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Yu-Ming Chang , Yung-Chun Li , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C16/10 , G11C11/56 , G11C16/08 , G11C16/26 , G11C16/34
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5648
摘要： A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.

4. 发明授权

US09025375B2 Memory disturb reduction for nonvolatile memory 有权
标题翻译：非易失性存储器的存储器干扰减少
公开(公告)号：US09025375B2
公开(公告)日：2015-05-05
申请号：US14060296
申请日：2013-10-22
申请人： Macronix International Co., Ltd.
发明人： Yu-Ming Chang , Yung-Chun Li , Hsing-Chen Lu , Hsiang-Pang Li , Cheng-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C16/04 , G11C16/34 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , G11C16/0483 , G11C16/16 , G11C16/3427
摘要： Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.
摘要翻译：描述了支持减少非易失性存储器的程序干扰的技术。三/二维NAND阵列包括被分成多个页组的多页。允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元的三/二维NAND阵列。同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

5. 发明授权

US11640255B2 Memory device and operation method thereof 有权
公开(公告)号：US11640255B2
公开(公告)日：2023-05-02
申请号：US17518624
申请日：2021-11-04
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Wei-Chen Wang , Ting-Hsuan Lo , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F12/00 , G06F3/06
摘要： Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

6. 发明授权

US11526285B2 Memory device for neural networks 有权
公开(公告)号：US11526285B2
公开(公告)日：2022-12-13
申请号：US16564066
申请日：2019-09-09
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Wei-Chen Wang , Hung-Sheng Chang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06 , G06N3/04
摘要： A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

7. 发明授权

US10671296B2 Management system for managing memory device and management method for managing the same 审中-公开
公开(公告)号：US10671296B2
公开(公告)日：2020-06-02
申请号：US15672430
申请日：2017-08-09
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Hung-Sheng Chang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06 , G06F12/02 , G11C7/04
摘要： Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

8. 发明申请

US20190073136A1 MEMORY CONTROLLING METHOD, MEMORY CONTROLLING CIRCUIT AND MEMORY SYSTEM 审中-公开
公开(公告)号：US20190073136A1
公开(公告)日：2019-03-07
申请号：US15696325
申请日：2017-09-06
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Hung-Sheng Chang , Hsiang-Pang Li , Tse-Yuan Wang , Che-Wei Tsao , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06
摘要： A memory controlling method, a memory controlling circuit and a memory system are provided. A memory includes a plurality of memory chips. The memory controlling method includes the following steps: The memory chips are grouped into at least two partner groups by a grouping unit. A quantity of the memory chips in each of the partner groups is at least two. At least one of the memory chips in each of the partner groups is required to serve a reading request or a writing request by a processing unit.

9. 发明授权

US09754637B2 Erasing method and memory device using the same 有权
公开(公告)号：US09754637B2
公开(公告)日：2017-09-05
申请号：US15212340
申请日：2016-07-18
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Yu-Ming Chang , Hsiang-Pang Li , Hsin-Yu Chang , Chien-Chung Ho , Yuan-Hao Chang
IPC分类号： G11C7/00 , G11C16/00 , G11C16/16 , G11C16/14
CPC分类号： G11C7/00 , G11C16/14 , G11C16/16
摘要： An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

10. 发明授权

US09547586B2 Metadata containers with indirect pointers 有权
标题翻译：具有间接指针的元数据容器
公开(公告)号：US09547586B2
公开(公告)日：2017-01-17
申请号：US13939948
申请日：2013-07-11
申请人： Macronix International Co., Ltd.
发明人： Hung-Sheng Chang , Cheng-Yuan Wang , Hsiang-Pang Li , Yuan-Hao Chang , Pi-Cheng Hsiu , Tei-Wei Kuo
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0238 , G06F12/0246 , G06F12/109 , G06F2212/1032 , G06F2212/7204 , G06F2212/7211
摘要： A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.
摘要翻译：提供了一种用于管理包括数据对象的文件系统的方法。数据对象，间接指针和源指针存储在具有地址并包含存储器可寻址单元的容器中。对象映射到相应容器的地址。特定容器中的间接指针指向存储相应对象的容器的地址。特定容器中的源指针指向特定容器中的对象映射到的容器的地址。将第一容器中的物体移动到第二容器。第一个容器中的源指针用于查找对象映射到的第三个容器。第三个容器中的间接指针被更新为指向第二个容器。第二个容器中的源指针被更新为指向第三个容器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式