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1. 发明申请

US20220399045A1 MEMORY DEVICE 有权
公开(公告)号：US20220399045A1
公开(公告)日：2022-12-15
申请号：US17777010
申请日：2020-11-17
申请人： METACNI CO., LTD.
发明人： Young Seung KIM , Seung Moon YOO , Min Chul JUNG
IPC分类号： G11C7/10
摘要： A memory device according to the present invention may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and a sorter that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data. First data, which is either data bit “0” or data bit “1”, can be input to the mergers in the form of a direct current of first logic, and second data, which is another piece of data, can be input to the mergers in the form of a pulse that changes from the first logic to the second logic and back to the first logic. When the first data is input, the sorter can allow the first data to pass as-is and output the first data as second output data in the form of a direct current of the first logic. When a first edge that changes from the second logic to the first logic is input, the sorter can delay the first edge by synchronizing the same with a rising edge or falling edge of the control pulse, and output the first edge as the second output data.

2. 发明申请

US20230015255A1 INTEGRATED COUNTER IN MEMORY DEVICE 有权
公开(公告)号：US20230015255A1
公开(公告)日：2023-01-19
申请号：US17783118
申请日：2020-12-03
申请人： METACNI CO., LTD.
发明人： Young Seung KIM , Mi Hwa LIM , Dong Min LIM
IPC分类号： G11C7/22 , G11C7/10 , G11C5/05
摘要： A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

3. 发明申请

US20230063400A1 LOW_POWERED MEMORY DEVICE AND METHOD OF CONTROLLING POWER OF THE SAME 有权
公开(公告)号：US20230063400A1
公开(公告)日：2023-03-02
申请号：US17865381
申请日：2022-07-14
申请人： METACNI CO., LTD.
发明人： Young Seung KIM , Min Chul JUNG , Scott Seung Moon YOO
IPC分类号： G11C7/10 , G11C7/12 , G11C8/08 , G11C5/02
摘要： The memory device according to an embodiment may comprise a memory cell array in which memory cells of a latch structure are connected in a matrix form to word lines and bit lines and a peripheral circuit configured to supply a first voltage to the memory cells only in a developing section of a read operation for the memory cells and supply a second voltage which maintains data of the memory cells and lower than the first voltage in other sections. The peripheral circuit may be configured to supply the second voltage to the memory cells in all sections of a write operation for the memory cells.

4. 发明申请

US20220328095A1 MEMORY DEVICE, AND METHOD FOR DRIVING MEMORY 有权
公开(公告)号：US20220328095A1
公开(公告)日：2022-10-13
申请号：US17641500
申请日：2020-08-25
申请人： METACNI CO.,LTD.
发明人： Young Seung KIM , Seung Moon YOO , Min Chul JUNG
IPC分类号： G11C11/419
摘要： A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

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