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1. 发明授权

US10014062B2 Apparatus and methods for determining a pass/fail condition of a memory device 有权
公开(公告)号：US10014062B2
公开(公告)日：2018-07-03
申请号：US15084943
申请日：2016-03-30
申请人： MICRON TECHNOLOGY, INC.
发明人： Violante Moschiano , Giovanni Santin
IPC分类号： G11C16/34 , G11C11/56 , G11C16/06 , G11C16/24 , G11C16/10 , G11C16/00 , G11C29/04
CPC分类号： G11C16/3436 , G11C11/56 , G11C11/5628 , G11C16/00 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C16/3481 , G11C2029/0409
摘要： Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.

2. 发明授权

US09779839B2 Methods for providing redundancy in a memory array comprising mapping portions of data associated with a defective address 有权
公开(公告)号：US09779839B2
公开(公告)日：2017-10-03
申请号：US14940327
申请日：2015-11-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
IPC分类号： G11C29/00 , G11C7/00 , G11C16/04
CPC分类号： G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
摘要： Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data.

3. 发明申请

US20170235637A1 HIGH PERFORMANCE MEMORY CONTROLLER 审中-公开
公开(公告)号：US20170235637A1
公开(公告)日：2017-08-17
申请号：US15583678
申请日：2017-05-01
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1048 , G06F11/1068 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
摘要： A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

4. 发明授权

US09639420B2 High performance memory controller 有权
公开(公告)号：US09639420B2
公开(公告)日：2017-05-02
申请号：US14657878
申请日：2015-03-13
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC分类号： G11C29/00 , G06F11/10 , H03M13/37 , G11C29/02 , G11C29/52 , H03M13/11 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1048 , G06F11/1068 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
摘要： A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

5. 发明申请

US20160266966A1 HIGH PERFORMANCE MEMORY CONTROLLER 有权
标题翻译：高性能内存控制器
公开(公告)号：US20160266966A1
公开(公告)日：2016-09-15
申请号：US14657878
申请日：2015-03-13
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC分类号： G06F11/10 , H03M13/11 , G11C29/52
CPC分类号： G06F11/1076 , G06F11/1048 , G06F11/1068 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
摘要： A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
摘要翻译：存储器件包括包括缓冲器数据的存储器阵列。存储器装置还包括存储器控制器。存储器控制器包括纠错码（ECC）组件。存储器控制器还接收与ECC组件分析的状态命令和与数据质量有关的指示。基于状态值，存储器控制器经由ECC组件利用多个纠错技术之一来校正错误（例如，软状态，校准等）。

6. 发明申请

US20160071619A1 METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY 有权
标题翻译：在存储器中提供冗余的方法和装置
公开(公告)号：US20160071619A1
公开(公告)日：2016-03-10
申请号：US14940327
申请日：2015-11-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
摘要： Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
摘要翻译：用于在存储器中提供冗余的方法包括将与被确定为指示缺陷存储器单元的存储器的地址相关联的第一数据的一部分映射到存储器阵列的冗余区域的地址，以及将第二数据写入存储器阵列，其中将第二数据的一部分写入与被确定为指示用于第一数据的有缺陷的存储器单元的存储器的地址相关联的存储器阵列的列。装置包括存储器控制电路，其被配置为响应于指示有缺陷的存储器单元的地址来选择一部分数据以映射到不同的地址，并且还被配置为为特定行选择不同于不同行的数据的不同部分，其中特定行和不同行与存储器阵列的相同列相关联。

7. 发明申请

US20150248937A1 NON-VOLATILE MEMORY PROGRAMMING 有权
标题翻译：非易失性存储器编程
公开(公告)号：US20150248937A1
公开(公告)日：2015-09-03
申请号：US14715169
申请日：2015-05-18
申请人： Micron Technology, Inc.
发明人： Paul D. Ruby , Violante Moschiano , Giovanni Santin
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.
摘要翻译：一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。这种方法将电压施加到与已编程其它存储器单元组之后，以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。描述包括附加存储器件和方法的其它实施例。

8. 发明申请

US20150063031A1 DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE 有权
公开(公告)号：US20150063031A1
公开(公告)日：2015-03-05
申请号：US14538020
申请日：2014-11-11
申请人： MICRON TECHNOLOGY, INC.
发明人： Tommaso Vali , Giovanni Santin , Massimo Rossini , William H. Radke , Violante Moschiano
IPC分类号： G11C16/10 , G11C16/26 , G11C16/34
CPC分类号： G11C16/3436 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/3418 , G11C16/3422
摘要： A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

9. 发明授权

US10671479B2 High performance memory controller 审中-公开
公开(公告)号：US10671479B2
公开(公告)日：2020-06-02
申请号：US16105305
申请日：2018-08-20
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC分类号： H03M13/00 , G06F11/10 , G11C29/52 , H03M13/37 , G11C29/02 , H03M13/29 , H03M13/11 , G11C29/04 , H03M13/45
摘要： A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

10. 发明授权

US10055293B2 High performance memory controller 有权
公开(公告)号：US10055293B2
公开(公告)日：2018-08-21
申请号：US15583678
申请日：2017-05-01
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC分类号： G11C29/00 , G06F11/10 , H03M13/37 , G11C29/02 , G11C29/52 , H03M13/11 , G11C29/04 , H03M13/45
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/1076 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/2906 , H03M13/3715 , H03M13/45
摘要： A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

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