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1. 发明授权

US07071851B1 Techniques for implementing non-uniform constraints in modulation encoded data 失效
标题翻译：在调制编码数据中实现非均匀约束的技术
公开(公告)号：US07071851B1
公开(公告)日：2006-07-04
申请号：US11048597
申请日：2005-01-31
申请人： Mario Blaum , Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Ksenija Lakovic , Thomas Mittelholzer , Travis Oenning , Bruce A. Wilson
发明人： Mario Blaum , Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Ksenija Lakovic , Thomas Mittelholzer , Travis Oenning , Bruce A. Wilson
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1426
摘要： Non-uniform modulation encoding techniques are provided to prevent data from containing bit patterns that are prone to errors during read back. Modulation encoding is performed on a data stream to remove error prone bit patterns. Unconstrained data, such as error check parity, that is inserted into the modulated data stream may contain error prone bit patterns. Stricter modulation constraints are enforced on bits that are next to the unconstrained data, than on the remaining bits. By enforcing stricter modulation constraints on these bits, an entire data bit stream can have a desired modulation constraint.
摘要翻译：提供非均匀调制编码技术以防止数据包含在回读期间容易出错的位模式。对数据流执行调制编码以消除容易出错的位模式。插入调制数据流的无约束数据（如错误校验奇偶校验）可能包含易错位模式。对于与无约束数据相邻的位，对其余位执行更严格的调制约束。通过对这些位执行更严格的调制约束，整个数据比特流可以具有期望的调制限制。

2. 发明授权

US07064687B1 Techniques for modulating data using short block encoders 失效
标题翻译：使用短块编码器调制数据的技术
公开(公告)号：US07064687B1
公开(公告)日：2006-06-20
申请号：US11048273
申请日：2005-01-31
申请人： Mario Blaum , Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Ksenija Lakovic , Thomas Mittelholzer , Travis Oenning , Bruce A. Wilson
发明人： Mario Blaum , Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Ksenija Lakovic , Thomas Mittelholzer , Travis Oenning , Bruce A. Wilson
IPC分类号： H03M7/00
CPC分类号： H03M13/53 , G11B20/10009 , G11B20/1426 , G11B20/1809 , H03M5/145
摘要： Techniques are provided for applying modulation constraints to data streams using a short block encoder. A short block encoder encodes a subset of the bits in a data stream. Then, the even and odd interleaves in a data stream are separated into two data paths. A first modulation encoder encodes the even interleave according to a first modulation constraint. A second modulation encoder encodes the odd interleave according to a second modulation constraint, which in general coincides with the modulation constraint for even interleave.
摘要翻译：提供了使用短块编码器将调制限制应用于数据流的技术。短块编码器编码数据流中的比特的子集。然后，数据流中的偶数和奇数交织被分成两个数据路径。第一调制编码器根据第一调制约束编码偶数交织。第二调制编码器根据第二调制约束对奇数交织进行编码，其通常与用于偶数交织的调制约束一致。

3. 发明授权

US07030789B1 Techniques for applying modulation constraints to data using periodically changing symbol mappings 有权
标题翻译：使用周期性变化的符号映射对数据应用调制约束的技术
公开(公告)号：US07030789B1
公开(公告)日：2006-04-18
申请号：US11002970
申请日：2004-12-01
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Thomas Mittelholzer , Travis Oenning
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Thomas Mittelholzer , Travis Oenning
IPC分类号： H03M7/02
CPC分类号： H03M7/04 , G06F11/08 , G11B20/1426 , G11B2020/1473 , H03M5/145 , H03M7/06 , H03M13/31
摘要： Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.
摘要翻译：提供了通过使用周期性变化的符号映射来替代某些禁止的易错数据模式来向数据应用调制约束的技术。最初，使用基本转换技术将第一基站中的用户数据映射到第二基站的整数。第二个碱基中的整数对应于符号。随后，执行周期性地改变的符号映射，其中在基本转换期间产生的禁止符号被映射到允许的符号。周期性变化的符号映射发生在多个阶段，禁止符号在每个阶段都不同。在一些实施例中，所生成的数据由预编码器处理。

4. 发明申请

US20090027242A1 HIGH-RATE RLL ENCODING 有权
标题翻译：高速RLL编码
公开(公告)号：US20090027242A1
公开(公告)日：2009-01-29
申请号：US12185095
申请日：2008-08-03
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1426 , G11B2020/1446 , G11B2020/1473 , G11B2220/90 , G11B2220/956
摘要： An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.
摘要翻译：未编码的m位数据输入序列被分成n位块和m-n位块。 n位的块被划分为第一组n + 1个编码比特，其中第一组的P1个子块中的至少一个满足G，M和I约束。第一组n + 1个编码比特被映射到n + 1编码比特的第二组，其中第二组的P2子块中的至少一个在1 /（1 + D2）预编码之后产生至少Q1个转换。第二组n + 1编码比特被分成P3编码子块，并且P3编码子块在（mn）/ s个未编码符号之间进行交织，以形成第（m + 1）比特的输出序列码字，然后存储在数据存储介质。

5. 发明授权

US06901119B2 Method and apparatus for implementing soft-input/soft-output iterative detectors/decoders 失效
标题翻译：用于实现软输入/软输出迭代检测器/解码器的方法和装置
公开(公告)号：US06901119B2
公开(公告)日：2005-05-31
申请号：US09792325
申请日：2001-02-22
申请人： Roy Daron Cideciyan , Jonathan Darrel Coker , Ajay Dholakia , Evangelos S. Eleftheriou , Richard Leo Galbraith , Thomas Mittelholzer , David James Stanek
发明人： Roy Daron Cideciyan , Jonathan Darrel Coker , Ajay Dholakia , Evangelos S. Eleftheriou , Richard Leo Galbraith , Thomas Mittelholzer , David James Stanek
IPC分类号： G11B20/10 , G11B20/18 , H03M13/11 , H03M13/41 , H03M13/45 , H04L27/06 , H03D1/00
CPC分类号： H03M13/3905 , G11B20/10046 , G11B20/10055 , G11B20/10212 , G11B20/10287 , G11B20/10296 , G11B20/18 , H03M13/1102 , H03M13/2957 , H03M13/3961 , H03M13/4107 , H03M13/45 , H03M13/6331 , H03M13/6343 , H03M13/6502
摘要： A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.
摘要翻译：提供了一种用于实现软输入软输出迭代检测器/解码器的方法和装置。软输入信息直接添加到输入信道样本。使用检测器网格来检测包括所接收的输入信道样本与附加的软输入信息的输入信号。转换分支度量项，以在添加的比较选择（ACS）单元之后用所添加的软输入信息和一些常数项来移位所有时变项。随着添加的软输入信息和移位常数项的移位的时变项直接添加到状态度量项。软输入信息直接添加到输入信道样本，并且分支度量的计算不受影响。这允许优化双最大检测器和软输入软输出维特比检测器架构，以最小化硬件复杂性和功耗。

6. 发明申请

US20090089645A1 DATA STORAGE SYSTEMS 审中-公开
标题翻译：数据存储系统
公开(公告)号：US20090089645A1
公开(公告)日：2009-04-02
申请号：US12058151
申请日：2008-03-28
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： Method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream in dependence on the output bit stream and the data block. An error correction decoder connected to the post processor generates a second error corrected bit stream in dependence on the first error corrected bit stream and also generates a checksum in dependence of the second error corrected bit stream. A feedback path supplies from the error correction decoder to the post processor pinning data indicative of locations of correct bits in the second error corrected bit stream in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave. The post processor regenerates the first error corrected bit stream in dependence on the pinning data received from the error correction decoder.
摘要翻译：用于在数据存储系统中解码数据的方法和装置。在操作中，检测器根据从数据存储系统的存储子系统接收的数据块产生输出位流。连接到检测器的后处理器根据输出比特流和数据块生成第一纠错比特流。连接到后处理器的纠错解码器根据第一纠错比特流产生第二纠错比特流，并且还根据第二纠错比特流产生校验和。在校验和指示第二纠错比特流中的错误并且校正的第二错误的情况下，反馈路径从错误校正解码器向后处理器提供钉扎指示第二纠错比特流中的正确比特的位置的数据位流包括至少一个正确的交错。后处理器根据从纠错解码器接收到的钉扎数据重新生成第一纠错比特流。

7. 发明授权

US07395482B2 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US07395482B2
公开(公告)日：2008-07-01
申请号：US10739966
申请日：2003-12-18
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，调制解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的预编码应用于调制编码比特流。然而，该预编码仅应用于位流的选定部分。还可以存在一个置换步骤，其中在由预编码器施加预编码之前，该位序列在调制编码器之后被置换。解码器子系统以相反的方式运行。

8. 发明授权

US07193802B2 Apparatus for providing dynamic equalizer optimization 失效
标题翻译：用于提供动态均衡器优化的装置
公开(公告)号：US07193802B2
公开(公告)日：2007-03-20
申请号：US10809230
申请日：2004-03-25
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning , Michael J. Ross , David J. Stanek
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning , Michael J. Ross , David J. Stanek
IPC分类号： G11B5/09 , G11B5/035 , H03K5/139
CPC分类号： G11B5/035
摘要： An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.
摘要翻译：公开了一种用于提供动态均衡器优化的装置。本发明通过提供均衡器系数更新来解决上述问题，所述均衡器系数更新收敛于与直接方法相同的解决方案，而不必首先将已知模式写入盘或需要任何已经写入盘中的数据的任何知识。自适应余弦函数可用于仅修改DFIR抽头集，仅修改余弦均衡器的j和k参数，或者修改DFIR滤波器的抽头集合和余弦均衡器的j和k参数。可以使用诸如LMS算法的另一种算法来修改未被余弦算法修改的参数。

9. 发明授权

US09037951B2 Data management in solid state storage systems 有权
标题翻译：固态存储系统中的数据管理
公开(公告)号：US09037951B2
公开(公告)日：2015-05-19
申请号：US13516627
申请日：2010-12-16
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadas , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadas , Thomas Mittelholzer
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1008 , G06F11/1012 , G06F11/1068 , G06F11/108
摘要： Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.
摘要翻译：提供了用于控制数据管理操作的方法和装置，包括固态存储系统的固态存储中的数据的存储。输入数据存储在固态存储器中的连续的数据写入位置组中。每个组包括在固态存储器的多个逻辑子部分的每一个中的一组写入位置。要存储在每个组中的输入数据根据第一和第二线性纠错码进行编码。通过从输入数据中构成数据符号的行和列的逻辑阵列，来构成编码。行和列分别根据第一和第二线性纠错码编码以产生编码阵列，其中所有行对应于相应的第一码字和列对应于相应的第二码字。

10. 发明授权

US08276038B2 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US08276038B2
公开(公告)日：2012-09-25
申请号：US11833274
申请日：2007-08-03
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03M7/46 , H03M13/03 , G11B20/18
CPC分类号： H03M5/145 , G11B20/1833 , G11B2020/1836 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/6343
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，信道解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的前面应用于调制编码比特流。然而，上述内容仅适用于位流的选定部分。还可以存在一个置换步骤，其中比特序列在调制编码器之前被预编码器施加之前被置换。解码器子系统以相反的方式运行。

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