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    • 9. 发明授权
    • Distributed processing in a cryptography acceleration chip
    • 密码加速芯片中的分布式处理
    • US07600131B1
    • 2009-10-06
    • US09610798
    • 2000-07-06
    • Suresh KrishnaChristopher OwenDerrick C. LinJoseph J. TardoPatrick Law
    • Suresh KrishnaChristopher OwenDerrick C. LinJoseph J. TardoPatrick Law
    • H04L9/00
    • H04L63/0428G06F9/3879G06F21/604G06F21/72G06F2207/7219H04L63/0485H04L63/164
    • Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.
    • 提供了一种用于加密加速器芯片的架构,其允许比先前的现有技术设计显着的性能改进。 在各种实施例中,架构能够通过多个密码引擎并行处理分组,并且包括被配置为有效地处理数据分组的加密/解密的分类引擎。 密码学加速芯片可以被合并在网络线卡或服务模块上,并用于将单个计算机连接到WAN,大型企业网络以及服务于广泛地理区域(例如,城市)的网络的应用。 本发明提供了相对于现有技术设计的改进的性能,其中局部存储器要求大大降低,在某些情况下不需要额外的外部存储器。 在一些实施例中,本发明实现IPSec协议数据分组的持续全双工千兆比特速率安全处理。
    • 10. 发明授权
    • Probabilistic cryptographic processing method
    • 概率密码处理方法
    • US5235644A
    • 1993-08-10
    • US546614
    • 1990-06-29
    • Amar GuptaButler W. LampsonWilliam R. HaweJoseph J. TardoCharles W. KaufmanMark F. KempfMorrie GasserB. J. Herbison
    • Amar GuptaButler W. LampsonWilliam R. HaweJoseph J. TardoCharles W. KaufmanMark F. KempfMorrie GasserB. J. Herbison
    • H04L29/02
    • H04L29/02
    • A decryption method, and associated cryptographic processor, for performing in-line decryption of information frames received from a communication network through a first in-line processing stage. As an information packet is streamed into the cryptographic processor, a determination is made to an acceptable level of probability whether the packet contains data that should be decrypted. The decision whether or not decrypt is made by analyzing the incoming packet header, recognizing a limited number of packet formats, and further parsing the packet to locate any encrypted data and to make sure that the packet is not a segment of a larger message. Falsely decrypted packets are looped back through the cryptographic processor, to regenerate the data that was falsely decrypted. Decryption and encryption are performed in such a manner that a false decryption is completely reversible without loss of data. Special treatment is provided for packets containing data that cannot be divided into an integral number of standard blocks required for decryption processing.
    • 一种解密方法和相关联的密码处理器,用于通过第一串联处理级来执行从通信网络接收的信息帧的在线解密。 当信息分组被流传输到密码处理器中时,确定分组是否包含应被解密的数据的可接受概率水平。 通过分析进入的分组报头,识别有限数量的分组格式以及进一步解析分组以定位任何加密的数据并确保分组不是更大的消息的分段来进行解密的决定。 虚假解密的数据包通过密码处理器环回,以重新生成被错误解密的数据。 执行解密和加密,使得假解密完全可逆而不丢失数据。 对于包含不能被分解为解密处理所需的整数个标准块的数据的数据包,提供特殊处理。