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1. 发明申请

US20180316487A1 APPARATUS AND METHOD FOR PERFORMING OPERATION BEING SECURE AGAINST SIDE CHANNEL ATTACK 审中-公开
公开(公告)号：US20180316487A1
公开(公告)日：2018-11-01
申请号：US15861773
申请日：2018-01-04
申请人： SAMSUNG SDS CO., LTD.
发明人： Kyu-Young CHOI , Duk-Jae MOON , Hyo-Jin YOON , Ji-Hoon CHO
IPC分类号： H04L9/00 , G06F7/72 , H04L9/08
CPC分类号： H04L9/003 , G06F1/03 , G06F7/723 , G06F7/725 , G06F21/755 , G06F2207/7219 , H04L9/3252
摘要： An apparatus and method for performing operation being secure against side channel attack are provided. The apparatus and method generate values equal to values obtained through an exponentiation operation or a scalar multiplication operation of a point using values extracted from previously generated parameter candidate value sets and an operation secure against side-channel attack, thereby improving security against side-channel attack without degrading performance.

2. 发明授权

US08544077B2 Internet protocol telephony security architecture 有权
公开(公告)号：US08544077B2
公开(公告)日：2013-09-24
申请号：US12490124
申请日：2009-06-23
申请人： Eric J. Sprunk , Paul Moroney , Alexander Medvinsky , Steven E. Anderson , Jonathan A. Fellows
发明人： Eric J. Sprunk , Paul Moroney , Alexander Medvinsky , Steven E. Anderson , Jonathan A. Fellows
IPC分类号： G06F7/04
CPC分类号： H04L29/06027 , G06F12/1408 , G06F21/606 , G06F2207/7219 , G06F2211/008 , G06F2221/2129 , H04L9/083 , H04L9/0841 , H04L9/3213 , H04L9/3263 , H04L63/0435 , H04L63/0442 , H04L63/061 , H04L63/062 , H04L63/0807 , H04L63/12 , H04L65/1043
摘要： A secure Internet Protocol (IP) telephony system, apparatus, and methods are disclosed. Communications over an IP telephony system can be secured by securing communications to and from a Cable Telephony Adapter (CTA). The system can include one or more CTAs, network servers, servers configured as signaling controllers, key distribution centers (KDC), and can include gateways that couple the IP telephony system to a Public Switched Telephone Network (PSTN). Each CTA can be configured as secure hardware and can be configured with multiple encryption keys that are used to communicate signaling or bearer channel communications. The KDC can be configured to periodically distribute symmetric encryption keys to secure communications between devices that have been provisioned to operate in the system and signaling controllers. The secure devices, such as the CTA, can communicate with other secure devices by establishing signaling and bearer channels that are encrypted with session specific symmetric keys derived from a symmetric key distributed by a signaling controller.

3. 发明申请

US20130159791A1 METHOD AND DEVICE FOR FAULT DETECTION 有权
标题翻译：用于故障检测的方法和装置
公开(公告)号：US20130159791A1
公开(公告)日：2013-06-20
申请号：US13715157
申请日：2012-12-14
申请人： Proton World International N.V. , STMicroelectronics (Rousset) SAS
发明人： Fabrice Marinet , Jean-Louis Modave , Gilles Van Assche , Ronny Van Keer
IPC分类号： G06F11/00
CPC分类号： G06F21/554 , G06F11/006 , G06F11/073 , G06F11/0751 , G06F11/079 , G06F21/755 , G06F2207/7219
摘要： The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.
摘要翻译：本公开涉及由处理装置实现的方法。该方法包括：基于存储在第一存储器设备中的一个或多个初始参数来执行计算功能的处理设备的第一执行。计算功能的执行产生至少一个初始参数的一个或多个修改值，其中在第一次执行期间，从第一存储器件读取一个或多个初始参数，并且将一个或多个修改值存储在第二存储设备。该方法还包括基于存储在第一存储器件中的一个或多个初始参数来执行计算功能的处理设备的第二执行。

4. 发明申请

US20110311041A1 CRYTOGRAPHICALLY TRANSFORMING DATA TEXT 有权
标题翻译： CRYTOGRAPHICALLY变换数据文本
公开(公告)号：US20110311041A1
公开(公告)日：2011-12-22
申请号：US12965689
申请日：2010-12-10
申请人： Bruce Murray
发明人： Bruce Murray
IPC分类号： H04L9/28
CPC分类号： H04L9/002 , G06F7/723 , G06F2207/7219 , H04L9/302
摘要： In the field of cryptography there is a need to reduce the time taken to cryptographically transform data text while maintaining the low memory requirements associated with conventional square-and-multiply modular exponentiation.A method of cryptographically transforming data text c comprises the step of generating an integer representation m of the data text c according to m=cd where d is a predetermined exponent. The step of generating the integer representation m includes generating a sequence of intermediate numbers, each intermediate number being based on two or fewer earlier numbers in the sequence. Generating a sequence of intermediate numbers includes retrieving a pre-stored instruction to determine which two or fewer earlier numbers in the sequence a given intermediate number is based on and the functional manipulation of the or each earlier number required to generate the given intermediate number.
摘要翻译：在密码学领域中，需要减少加密地转换数据文本所需的时间，同时保持与传统的平方和乘法模幂相关联的低存储器要求。密码变换数据文本c的方法包括根据m = cd生成数据文本c的整数表示m的步骤，其中d是预定指数。生成整数表示m的步骤包括生成中间数字序列，每个中间数字基于序列中两个或更少的较早的数字。生成中间数字序列包括检索预先存储的指令以确定给定中间数字中的序列中的两个或更少个较早的数字，以及生成给定中间数所需的或每个较早的数字的功能操作。

5. 发明申请

US20110246119A1 PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS 有权
标题翻译：将集成电路的电阻测试到侧面通道分析的过程
公开(公告)号：US20110246119A1
公开(公告)日：2011-10-06
申请号：US12750846
申请日：2010-03-31
申请人： Benoit FEIX , Georges GAGNEROT , Mylene ROUSSELLET , Vincent VERNEUIL
发明人： Benoit FEIX , Georges GAGNEROT , Mylene ROUSSELLET , Vincent VERNEUIL
IPC分类号： G01R31/00 , G06F19/00 , G06F7/52
CPC分类号： G06F21/556 , G06F7/723 , G06F21/75 , G06F2207/7219 , G09C1/00 , H04L9/003 , H04L9/005 , H04L9/302
摘要： A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.
摘要翻译：一种用于测试集成电路的过程包括在集成电路正在执行乘法时收集物理特性的一组点，将该点集合划分成多个侧向点子集，计算物理属性值的估计并且通过使用物理属性的值的估计来应用横向点的横向横向统计处理的步骤，以验证关于由集成电路操纵的变量的假设。

6. 发明授权

US07603558B2 Montgomery transform device, arithmetic device, IC card, encryption device, decryption device and program 有权
标题翻译：蒙哥马利变换装置，算术装置，IC卡，加密装置，解密装置和程序
公开(公告)号：US07603558B2
公开(公告)日：2009-10-13
申请号：US11151289
申请日：2005-06-14
申请人： Hideo Shimizu
发明人： Hideo Shimizu
IPC分类号： H04L9/32
CPC分类号： G06F7/728 , G06F2207/7219
摘要： According to an aspect of the invention, Montgomery arithmetic can be achieved while omitting division in an input stage. That is, the aspect of the invention is configured to obtain a Montgomery transform result m′ (=mR mod p) of n-bit from an input m of 2n-bit without using the division, with using Montgomery reduction and Montgomery multiplication instead of conventional mod arithmetic and the Montgomery transform. Accordingly, Montgomery arithmetic can be achieved while omitting the division in the input stage.
摘要翻译：根据本发明的一个方面，可以在省略输入阶段的划分的同时实现蒙哥马利算术。也就是说，本发明的方面被配置为从2n位的输入m获得n位的蒙哥马利变换结果m'（= mR mod p），而不使用除法，使用蒙哥马利减少和蒙哥马利乘法而不是传统的mod算法和蒙哥马利变换。因此，可以在省略输入阶段的划分的同时实现蒙哥马利算术。

7. 发明授权

US07600131B1 Distributed processing in a cryptography acceleration chip 有权
标题翻译：密码加速芯片中的分布式处理
公开(公告)号：US07600131B1
公开(公告)日：2009-10-06
申请号：US09610798
申请日：2000-07-06
申请人： Suresh Krishna , Christopher Owen , Derrick C. Lin , Joseph J. Tardo , Patrick Law
发明人： Suresh Krishna , Christopher Owen , Derrick C. Lin , Joseph J. Tardo , Patrick Law
IPC分类号： H04L9/00
CPC分类号： H04L63/0428 , G06F9/3879 , G06F21/604 , G06F21/72 , G06F2207/7219 , H04L63/0485 , H04L63/164
摘要： Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.
摘要翻译：提供了一种用于加密加速器芯片的架构，其允许比先前的现有技术设计显着的性能改进。在各种实施例中，架构能够通过多个密码引擎并行处理分组，并且包括被配置为有效地处理数据分组的加密/解密的分类引擎。密码学加速芯片可以被合并在网络线卡或服务模块上，并用于将单个计算机连接到WAN，大型企业网络以及服务于广泛地理区域（例如，城市）的网络的应用。本发明提供了相对于现有技术设计的改进的性能，其中局部存储器要求大大降低，在某些情况下不需要额外的外部存储器。在一些实施例中，本发明实现IPSec协议数据分组的持续全双工千兆比特速率安全处理。

8. 发明授权

US07430668B1 Protection of the configuration of modules in computing apparatus 有权
标题翻译：保护计算设备中模块的配置
公开(公告)号：US07430668B1
公开(公告)日：2008-09-30
申请号：US09913454
申请日：2000-02-15
申请人： Liqun Chen , David Chan
发明人： Liqun Chen , David Chan
IPC分类号： H04L9/00 , G06F15/177 , G06F11/30 , G06F21/00
CPC分类号： G06F11/2289 , G06F21/34 , G06F21/554 , G06F21/57 , G06F21/606 , G06F21/645 , G06F2207/7219 , G06F2211/008 , G06F2211/009 , G06F2221/2101 , G06F2221/2103 , G06F2221/2153
摘要： A method of protecting from modification computer apparatus comprising a plurality of functional modules by monitoring the configuration of functional modules within the computer apparatus. The method comprises: storing a module configuration of the computer apparatus; and checking the actual module configuration against the stored module configuration, and inhibiting function of the computer apparatus if the actual module configuration does not satisfactorily match the stored module configuration. Advantageously, the module configuration is stored on a security token, such as a smart card.
摘要翻译：通过监视计算机装置内的功能模块的配置来保护包括多个功能模块的修改计算机装置的方法。该方法包括：存储计算机装置的模块配置; 并且如果实际的模块配置不令人满意地匹配存储的模块配置，则根据存储的模块配置检查实际的模块配置，并且禁止计算机设备的功能。有利地，模块配置被存储在诸如智能卡的安全令牌上。

9. 发明授权

US07127620B2 Power analysis resistant coding device 有权
标题翻译：功率分析抗编码器
公开(公告)号：US07127620B2
公开(公告)日：2006-10-24
申请号：US10138656
申请日：2002-05-03
申请人： Gregor Boeckeler
发明人： Gregor Boeckeler
IPC分类号： G06F1/06 , G06F1/08 , G06F12/14 , H04K1/02 , H04L9/00 , G06F1/04
CPC分类号： H04L9/003 , G06F21/755 , G06F2207/7219 , G06K19/073 , H04L2209/08 , H04L2209/12
摘要： A coding device for implementing a cryptographic encryption and/or access authorization includes a data processing unit, a decoupling unit, a power supply interface, a main clock supply unit, and a power profile generator generating a power profile and superimposing it on a power profile of the data processing unit to prevent an attack by correlation analysis of the power profile.
摘要翻译：用于实现加密加密和/或访问授权的编码装置包括数据处理单元，去耦单元，电源接口，主时钟提供单元和产生功率分布的功率分布生成器，并将其叠加在功率剖面上的数据处理单元，以防止通过功率分布的相关分析的攻击。

10. 发明授权

US07069593B1 Device and method for making secure an integrated circuit 失效
标题翻译：用于安全集成电路的装置和方法
公开(公告)号：US07069593B1
公开(公告)日：2006-06-27
申请号：US09830378
申请日：1999-10-28
申请人： Eric Gerbault
发明人： Eric Gerbault
IPC分类号： G06F7/04 , G06F17/30 , G06K9/00 , H04K1/00 , H04L9/00
CPC分类号： G07F7/1008 , G06F21/556 , G06F21/755 , G06F2207/7219 , G06Q20/341 , G07F7/082
摘要： The present invention relates to an integrated circuit device containing a memory area, which comprises, on the one hand, a data memory and a program memory, and on the other hand, a program having N code blocks Bi (i=1, . . . , N). It also relates to a method for making such a device secure. The present invention is characterized in that the memory area has M replicas Cj (j=1, . . . , M) of x program code blocks Bi (x=1, . . . , N), which replicas reside at different addresses in said memory area, and in that said device has selection means for randomly selecting one replica Cj of at least one of the x blocks Bi, as a block replica to be used when executing said program. In particular, the present invention can be applied to smart cards.
摘要翻译：本发明涉及一种包含存储区域的集成电路装置，其一方面包括数据存储器和程序存储器，另一方面，具有N个码块Bi（i = 1，...，。，N）。它还涉及一种使这种装置安全的方法。本发明的特征在于，存储区域具有x个程序代码块Bi（x = 1，...，N）的M个副本C j（j = 1，...，M），该副本位于不同的地址所述存储区域，并且所述设备具有选择装置，用于随机选择x块Bi中的至少一个的一个副本Cj作为在执行所述程序时要使用的块副本。特别地，本发明可以应用于智能卡。

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