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1. 发明授权

US07747842B1 Configurable output buffer ganging for a parallel processor 有权
标题翻译：可配置的输出缓冲器组合用于并行处理器
公开(公告)号：US07747842B1
公开(公告)日：2010-06-29
申请号：US11311993
申请日：2005-12-19
申请人： Mark R. Goudy , Andrew J. Tao , Dominic Acocella
发明人： Mark R. Goudy , Andrew J. Tao , Dominic Acocella
IPC分类号： G06F9/50
CPC分类号： G06F9/5011
摘要： An output buffer in a multi-threaded processor is managed to store a variable amount of output data. Parallel threads produce a variable amount of output data. A controller is configured to determine how much output buffer space is needed per thread and how many threads can execute in parallel, given the available space in the output buffer. The controller also determines where each thread writes to in the output buffer.
摘要翻译：管理多线程处理器中的输出缓冲器以存储可变量的输出数据。并行线程产生可变量的输出数据。控制器被配置为确定在输出缓冲区中可用空间的情况下，每个线程需要多少输出缓冲区空间以及并行执行多少个线程。控制器还确定每个线程在输出缓冲区中写入的位置。

2. 发明授权

US07750915B1 Concurrent access of data elements stored across multiple banks in a shared memory resource 有权
标题翻译：并发访问存储在共享内存资源中的多个存储区的数据元素
公开(公告)号：US07750915B1
公开(公告)日：2010-07-06
申请号：US11312076
申请日：2005-12-19
申请人： Dominic Acocella , Mark R. Goudy
发明人： Dominic Acocella , Mark R. Goudy
IPC分类号： G06F15/167
CPC分类号： G06F12/0607 , G06F12/0846
摘要： Methods, apparatuses, and systems are presented for performing multiple concurrent accesses in a shared memory resource comprising storing a first group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the first group being stored in a data entry in a first bank; skipping at least one data entry in at least one bank after storing a last data element of the first group, to introduce an offset; following the offset, storing a second group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the second group being stored in a data entry in a second bank different from the first bank; and concurrently accessing the first data element of the first group from the first bank and the first data element of the second group from the second bank.
摘要翻译：呈现用于在共享存储器资源中执行多个并发访问的方法，装置和系统，包括在共享存储器资源中的跨多个存储体的数据条目中存储第一组数据元素，第一组的第一数据元素存储在第一银行的数据输入; 在存储第一组的最后一个数据元素之后，在至少一个存储体中跳过至少一个数据条目，以引入偏移量; 在偏移之后，将第二组数据元素存储在共享存储器资源中的多个存储体上的数据条目中，第二组的第一数据元素存储在与第一存储体不同的第二存储体中的数据条目中; 以及从第一组和第二组同时访问第一组的第一数据元素和第二组的第一数据元素。

3. 发明授权

US07366842B1 Creating permanent storage on the fly within existing buffers 有权
标题翻译：在现有缓冲区内即时创建永久存储
公开(公告)号：US07366842B1
公开(公告)日：2008-04-29
申请号：US11300874
申请日：2005-12-15
申请人： Dominic Acocella , Mark R. Goudy
发明人： Dominic Acocella , Mark R. Goudy
IPC分类号： G06F12/00
CPC分类号： G06F5/065
摘要： A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache window can be a subset of the entire circular buffer. If contents within the cache window are identified as persistent data, the locations corresponding to the persistent data can be identified as permanent memory locations. The position of the cache within the circular buffer can be frozen based on the permanent memory locations. A write mask can be used to maintain the contents of the permanent memory locations, while the remainder of the cache is configured as a temporary circular buffer. Operation of the cache returns to the entire circular buffer once the contents of the permanent memory locations no longer need to be maintained.
摘要翻译：具有活动高速缓存窗口的循环缓冲器可以被配置为临时分配活动高速缓存中的一个或多个位置作为永久存储器位置，以消除覆盖永久存储器位置的内容的可能性。缓存窗口可以是整个循环缓冲区的子集。如果缓存窗口内的内容被识别为持久性数据，则与永久数据相对应的位置可以被识别为永久存储器位置。可以基于永久存储器位置来冻结循环缓冲器内的缓存的位置。可以使用写掩码来维护永久性存储器位置的内容，而缓存的其余部分被配置为临时循环缓冲区。一旦永久性存储器位置的内容不再需要维护，高速缓存的操作将返回到整个循环缓冲区。

4. 发明授权

US08711156B1 Method and system for remapping processing elements in a pipeline of a graphics processing unit 有权
标题翻译：用于重新映射图形处理单元的流水线中的处理元件的方法和系统
公开(公告)号：US08711156B1
公开(公告)日：2014-04-29
申请号：US10956609
申请日：2004-09-30
申请人： Dominic Acocella , Timothy J. McDonald , Robert W. Gimby , Thomas H. Kong
发明人： Dominic Acocella , Timothy J. McDonald , Robert W. Gimby , Thomas H. Kong
IPC分类号： G06T1/20 , G06F12/10
CPC分类号： G06T1/20 , G06F12/1063
摘要： A method and system for remapping units that are disabled to active units in a 3-D graphics pipeline. Specifically, in one embodiment, a method remaps processing elements in a pipeline of a graphics pipeline unit. Graphical input data are received. Then the number of enabled processing elements are determined from a plurality of processing elements. Each of the enabled processing elements are virtually addressed above a translator to virtually process the graphical input data. Then, the virtual addresses of each of the enabled processing elements are mapped to physical addresses of the enabled processing elements at the translator. The graphical input data are physically processed at the physical addresses of the enabled processing elements. In addition, each of the enabled processing elements are physically addressed below the translator to further process the graphical input data.
摘要翻译：一种用于重新映射单元的方法和系统，该单元被禁用于3-D图形管线中的活动单元。具体地，在一个实施例中，一种方法重新映射图形流水线单元的流水线中的处理元件。接收图形输入数据。然后，从多个处理元件确定使能的处理元件的数量。每个启用的处理元件在翻译器上虚拟地被处理以虚拟地处理图形输入数据。然后，每个启用的处理元件的虚拟地址被映射到翻译器处的启用的处理元件的物理地址。在启用的处理元件的物理地址上物理地处理图形输入数据。此外，每个启用的处理元件在翻译器的下面物理寻址，以进一步处理图形输入数据。

5. 发明授权

US06900810B1 User programmable geometry engine 有权
标题翻译：用户可编程几何引擎
公开(公告)号：US06900810B1
公开(公告)日：2005-05-31
申请号：US10727822
申请日：2003-12-03
申请人： Henry P. Moreton , Dominic Acocella , Justin Scott Legakis
发明人： Henry P. Moreton , Dominic Acocella , Justin Scott Legakis
IPC分类号： G06T1/00 , G06T15/00
CPC分类号： G06T15/005
摘要： A programmable geometry engine is described. One embodiment of the programmable geometry engine includes a programmable primitive engine configured to receive primitive commands that include information for processing vertex data using user-developed programs or subroutines. The programmable primitive engine also is configured to transmit program commands that include program pointers and data pointers. In addition, the programmable geometry engine includes a processing engine configured to receive the program commands. The processing engine is further configured to retrieve the user-developed programs or subroutines using the program pointers and to retrieve vertex data using the data pointers. Also, the processing engine is configured to process the vertex data based on instructions included in the user-developed programs or subroutines to produce processed vertex data and to transmit results to the programmable primitive engine.
摘要翻译：描述了可编程几何引擎。可编程几何引擎的一个实施例包括可编程原语引擎，其被配置为接收包括用于使用用户开发的程序或子例程处理顶点数据的信息的原始命令。可编程原语引擎还被配置为传送包括程序指针和数据指针的程序命令。另外，可编程几何引擎包括配置成接收程序命令的处理引擎。处理引擎还被配置为使用程序指针检索用户开发的程序或子程序，并使用数据指针检索顶点数据。此外，处理引擎被配置为基于包括在用户开发的程序或子程序中的指令来处理顶点数据，以产生经处理的顶点数据并将结果发送到可编程原始引擎。

6. 发明授权

US07400326B1 System and method for delivering multiple data streams via multiple buses 有权
标题翻译：通过多个总线传送多个数据流的系统和方法
公开(公告)号：US07400326B1
公开(公告)日：2008-07-15
申请号：US10944483
申请日：2004-09-16
申请人： Dominic Acocella , Robert W. Gimby , Thomas H. Kong , Andrew D. Bowen , Christopher J. Goodman , David C. Tannenbaum , Jeffrey B. Moskal , Steven Gregory Foster, Jr.
发明人： Dominic Acocella , Robert W. Gimby , Thomas H. Kong , Andrew D. Bowen , Christopher J. Goodman , David C. Tannenbaum , Jeffrey B. Moskal , Steven Gregory Foster, Jr.
IPC分类号： G06F13/14
CPC分类号： G06F13/4018
摘要： Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.
摘要翻译：通过两个总线传送两个数据流的系统和方法允许一个总线用于传送主要由另一个总线传送的数据流的所选元素。在输入重路由电路中，所选元素从第二数据流重新路由到第一数据流; 插入第二数据流中的令牌标识重新路由的元素的位置。修改的流由两条总线传输。接收电路在由占位符令牌识别的连续位置处将重新路由的数据元素重新插入到第二数据流中。

7. 发明授权

US07292239B1 Cull before attribute read 有权
标题翻译：在属性读取之前进行Cull
公开(公告)号：US07292239B1
公开(公告)日：2007-11-06
申请号：US10912930
申请日：2004-08-06
申请人： Henry Packard Moreton , Dominic Acocella , Robert W. Gimby , Thomas M. Ogletree , Christopher J. Goodman , Andrew D. Bowen , David C. Tannenbaum
发明人： Henry Packard Moreton , Dominic Acocella , Robert W. Gimby , Thomas M. Ogletree , Christopher J. Goodman , Andrew D. Bowen , David C. Tannenbaum
IPC分类号： G06T15/00 , G06T1/00 , G06T1/20 , G06F13/00
CPC分类号： G09G5/363 , G06T15/40 , G09G3/003 , G09G5/02 , G09G2360/121
摘要： The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.
摘要翻译：图形处理子系统的VPC单元和设置单元执行剔除操作。 VPC单元对属于特定标准的几何图元进行剔除操作，例如具有VPC单元数值范围内的属性。这种限制降低了VPC单元的复杂性。随着渲染复杂度的增加，通常会产生大量的小图元，尽管它的淘汰限制，VPC单元也可以剔除许多图元。 VPC单元还包括高速缓存，用于以先前针对顶点计算的剔除信息存储先前处理过的顶点的转换形式。为了最小化内存带宽，VPC单元首先检索用于剔除操作的顶点数据。完成剔除操作后，VPC单元仅在原始图元未被剔除时检索顶点的属性。 VPC单元对顶点属性应用透视校正因子。

8. 发明授权

US07233334B1 Storage buffers with reference counters to improve utilization 有权
标题翻译：具有参考计数器的存储缓冲区以提高利用率
公开(公告)号：US07233334B1
公开(公告)日：2007-06-19
申请号：US10955779
申请日：2004-09-29
申请人： Dominic Acocella , Henry Packard Moreton , Robert W. Gimby , Thomas H. Kong , Andrew D. Bowen
发明人： Dominic Acocella , Henry Packard Moreton , Robert W. Gimby , Thomas H. Kong , Andrew D. Bowen
IPC分类号： G06F13/14
CPC分类号： G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that improve utilization of storage buffers by overwriting data in them as soon as the data is no longer needed. An exemplary embodiment employs a counter to add each time a particular unit of data is needed by a circuit. The counter also subtracts each time the data is actually used by the circuit. When the counter reaches zero, upstream circuitry is checked to see if a command allowing the particular data to be overwritten has been issued. If it has, the command is not waited for, rather the data may be overwritten immediately. Embodiments of the present invention may also make use of one level of indirection to mask physical storage buffer locations from upstream circuitry. In this way, utilization can be improved.
摘要翻译：因此，本发明的实施例提供了一旦不再需要数据就可以通过覆盖其中的数据来提高存储缓冲器的利用率的电路，方法和装置。每一次电路需要特定的数据单元时，示例性实施例使用计数器来添加。每当电路实际使用数据时，计数器也会减去该值。当计数器达到零时，检查上游电路，看是否允许重写特定数据的命令。如果有，则不等待命令，而是立即覆盖数据。本发明的实施例还可以利用一级间接来从上游电路屏蔽物理存储缓冲器位置。这样可以提高利用率。

9. 发明授权

US07324105B1 Neighbor and edge indexing 有权
标题翻译：邻居和边缘索引
公开(公告)号：US07324105B1
公开(公告)日：2008-01-29
申请号：US10727679
申请日：2003-12-04
申请人： Henry P. Moreton , Dominic Acocella , Justin Scott Legakis
发明人： Henry P. Moreton , Dominic Acocella , Justin Scott Legakis
IPC分类号： G06T17/00 , G06T17/20
CPC分类号： G06T17/20
摘要： Method and apparatus for neighbor and edge indexing is described. A vertex is identified and assigned a reference. One-ring neighbor vertices of the vertex are identified. The reference is assigned to each of the one-ring neighbor vertices identified. An index to one of the one-ring neighbor vertices is assigned. The index is successively incremented to provide indices for each of the one-ring neighbor vertices remaining. Edge indexing follows as described above, with the vertex and its one-ring neighbors defining end points of edges. Additionally, offset indexing is described, and may be used for a consistent order of computation.
摘要翻译：描述了用于邻居和边缘索引的方法和装置。一个顶点被识别并分配一个参考。识别顶点的单环邻接顶点。引用被分配给所识别的每个单环邻居顶点。分配一个环形邻居顶点之一的索引。索引依次递增，为剩下的每一环邻近顶点提供索引。边缘索引如上所述，其中顶点及其单环邻居定义边缘的终点。另外，描述了偏移索引，并且可以用于一致的计算顺序。

10. 发明授权

US07196703B1 Primitive extension 有权
标题翻译：原始延伸
公开(公告)号：US07196703B1
公开(公告)日：2007-03-27
申请号：US10728047
申请日：2003-12-04
申请人： Henry P. Moreton , Dominic Acocella , Justin Scott Legakis , Craig Michael Wittenbrink
发明人： Henry P. Moreton , Dominic Acocella , Justin Scott Legakis , Craig Michael Wittenbrink
IPC分类号： G06T17/00 , G06T15/00 , G06T15/30 , G06T15/10
CPC分类号： G06T17/20
摘要： Method and apparatus for generating a primitive extension defining a generalized primitive is described. The primitive extension defines the connectivity and vertices used to specify a collection of connected primitives, such as a strip-type or fan-type generalized primitive. A generalized primitive includes a number of vertices where some of the vertices are shared with neighboring primitives. The primitive extension includes an originating primitive, vertex data, and connectivity information. The primitive extension provides a general interface for describing a variety of connected primitives.
摘要翻译：描述了用于生成定义广义基元的原始扩展的方法和装置。原始扩展定义了用于指定连接原语集合的连接性和顶点，例如条带类型或扇形广义原语。广义原语包括一些顶点，其中一些顶点与相邻基元共享。原始扩展包括始发原语，顶点数据和连接性信息。原始扩展提供了用于描述各种连接的原语的通用接口。

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