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1. 发明授权

US07259610B1 Static CMOS logic level shift circuit with a low logic input count high switching speed and low power dissipation 有权
标题翻译：具有低逻辑输入的静态CMOS逻辑电平移位电路计数高开关速度和低功耗
公开(公告)号：US07259610B1
公开(公告)日：2007-08-21
申请号：US10949111
申请日：2004-09-24
申请人： Marshall J. Bell , James R. Kozisek
发明人： Marshall J. Bell , James R. Kozisek
IPC分类号： H03L5/00
CPC分类号： H03K3/012 , H03K3/356165
摘要： A level shift circuit with high switching speed and low power dissipation is described. The circuit includes two short channel transistors, two long channel transistors, and two switching transistors. Short channel transistors are arranged to receive a high input voltage presenting relatively low impedance and low capacitance. Long channel transistors are arranged to receive a first voltage from the short channel transistors and provide an output voltage and an inverted output voltage, which are also employed to control the short channel transistors. A first switching transistor of the switching circuit enables the short channel and the long channel circuits to provide the output voltage based on a low input voltage and a logic input voltage. A second switching transistor enables the same circuits to provide the inverted output voltage based on the logic input voltage.
摘要翻译：描述了具有高开关速度和低功耗的电平移位电路。该电路包括两个短沟道晶体管，两个长沟道晶体管和两个开关晶体管。短沟道晶体管被布置成接收呈现相对低阻抗和低电容的高输入电压。长沟道晶体管布置成从短沟道晶体管接收第一电压并提供输出电压和反相输出电压，其也用于控制短沟道晶体管。开关电路的第一开关晶体管使得短沟道和长沟道电路能够基于低输入电压和逻辑输入电压来提供输出电压。第二开关晶体管使得相同的电路能够基于逻辑输入电压提供反相输出电压。

2. 发明授权

US07911437B1 Stacked amplifier with charge sharing 有权
标题翻译：具有电荷共享的堆叠放大器
公开(公告)号：US07911437B1
公开(公告)日：2011-03-22
申请号：US11580517
申请日：2006-10-13
申请人： Marshall J. Bell
发明人： Marshall J. Bell
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3685 , G09G2310/0248 , G09G2310/0297 , G09G2330/021
摘要： Column drivers for graphics displays can be arranged as stacked amplifiers with various switching circuits arranged in a charge sharing topology. The apparatus includes an upper and lower amplifier circuit, an input switching circuit, and an output switching circuit. The upper and lower amplifier circuits drive column lines can be swapped during operation by the input and output switching circuits. During a charge share operation, the outputs of the amplifiers are coupled to a common voltage via the output switching circuit, while the transistors from the output stage of each amplifier is reconfigured for charge sharing. Minimally sized transistors are utilized inside the output stage of the amplifiers for charge share configuration. Since the existing transistors from the output stage are utilized for the charge sharing operation, additional space savings and power reductions can be realized.
摘要翻译：用于图形显示器的列驱动器可以被布置为具有以电荷共享拓扑布置的各种开关电路的堆叠放大器。该装置包括上下放大器电路，输入开关电路和输出开关电路。驱动列线的上下放大器电路可在输入和输出开关电路工作期间互换。在电荷共享操作期间，放大器的输出经由输出开关电路耦合到公共电压，而来自每个放大器的输出级的晶体管被重新配置用于电荷共享。在放大器的输出级内使用最小尺寸的晶体管用于电荷共享配置。由于来自输出级的现有晶体管用于电荷共享操作，因此可以实现额外的空间节省和功率降低。

3. 发明授权

US06970152B1 Stacked amplifier arrangement for graphics displays 有权
标题翻译：用于图形显示的堆叠放大器布置
公开(公告)号：US06970152B1
公开(公告)日：2005-11-29
申请号：US10287900
申请日：2002-11-05
申请人： Marshall J. Bell , Christopher A. Ludden , Richard Alexander Erhart
发明人： Marshall J. Bell , Christopher A. Ludden , Richard Alexander Erhart
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3688 , G09G3/3655 , G09G2310/0235 , G09G2330/023
摘要： A column driver for a graphics display has reduced power consumption by sharing power between upper and lower column amplifiers. The upper column amplifier operates over an upper supply range, while the lower column amplifier operates over a lower supply range. The upper and lower amplifiers have the substantially the same quiescent operating current such that the total operating current for the column drivers in the graphics display is reduced by a factor of two. Each column amplifier can be driven over half of the power-supply range such that lower voltage amplifiers may be employed for the column driver amplifiers.
摘要翻译：用于图形显示的列驱动器通过在上下列放大器之间共享功率来降低功耗。上列放大器在较高电源范围内工作，而下列放大器在较低电源范围内工作。上部和下部放大器具有基本上相同的静态工作电流，使得图形显示器中的列驱动器的总工作电流减少了2倍。每个列放大器可以驱动超过一半的电源范围，使得可以使用较低电压放大器用于列驱动放大器。

4. 发明授权

US07355582B1 Switched capacitor cyclic DAC in liquid crystal display column driver 有权
标题翻译：开关电容循环DAC在液晶显示器列驱动
公开(公告)号：US07355582B1
公开(公告)日：2008-04-08
申请号：US10850972
申请日：2004-05-21
申请人： Marshall J. Bell
发明人： Marshall J. Bell
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2320/0285 , G09G2320/041 , G09G2320/0673
摘要： A method and circuit for providing analog voltages to an LCD panel based on digital voltages. A gamma curve defining a relationship between the applied voltage and a luminescence of the liquid crystals is implemented in a timing controller through a look-up table, an algorithm, and the like. The digital grey level values provided by the timing controller are converted to analog voltages by a linear switched capacitor cyclic digital-analog-converter (DAC) in each column driver. Switches are set in a different configuration for each conversion cycle allowing charges to be accumulated in capacitors based on a value of an input bit. The DAC converts starting with a least significant bit. Linear operation allows handling of larger amounts of data without increasing circuit size significantly. A capacitor mismatch error may be reduced significantly by swapping capacitor configuration every other cycle or frame.
摘要翻译：一种基于数字电压向LCD面板提供模拟电压的方法和电路。通过查找表，算法等在定时控制器中实现限定施加的电压和液晶的发光之间的关系的伽马曲线。由定时控制器提供的数字灰度值通过每列驱动器中的线性开关电容器循环数模转换器（DAC）转换为模拟电压。开关设置在每个转换周期的不同配置中，允许根据输入位的值将电荷累积在电容器中。 DAC以最低有效位开始转换。线性操作允许处理更大量的数据，而不会显着增加电路尺寸。通过每隔一个周期或帧交换电容器配置，可能会显着降低电容器失配误差。

5. 发明授权

US07088163B1 Circuit for multiplexing a tapped differential delay line to a single output 有权
标题翻译：用于将抽头的差分延迟线复用到单个输出的电路
公开(公告)号：US07088163B1
公开(公告)日：2006-08-08
申请号：US10949121
申请日：2004-09-24
申请人： Marshall J. Bell , James R. Kozisek
发明人： Marshall J. Bell , James R. Kozisek
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K5/133 , H03K2005/00058 , H03K2005/00176
摘要： A method and circuit to adjust timing between received differential data and clock signals to compensate for differences between transmission paths of data and clock signals. According to one embodiment, a timing adjustment circuit includes a decoder, a differential delay stage and a converter stage. The decoder is arranged to select one of the differential tri-state buffers, which provides the signal with a selected delay to a differential-to-single-ended converter. The converter provides properly a timing-adjusted signal to other circuits for further processing. Two current sources may be employed instead of resistive loads for the converter stage resulting in increased operating frequency and decreased power dissipation.
摘要翻译：一种用于调整接收的差分数据和时钟信号之间的定时以补偿数据和时钟信号的传输路径之间的差异的方法和电路。根据一个实施例，定时调整电路包括解码器，差分延迟级和转换器级。解码器被布置为选择差分三态缓冲器中的一个，其将信号提供到差分到单端转换器的选定延迟。转换器正确地提供了一个定时调整信号到其他电路进行进一步处理。可以采用两个电流源来代替转换器级的电阻负载，从而导致工作频率的增加和功耗的降低。

6. 发明授权

US06762646B1 Modified folded cascode amplifier 有权
标题翻译：改进的折叠共源共栅放大器
公开(公告)号：US06762646B1
公开(公告)日：2004-07-13
申请号：US10263571
申请日：2002-10-02
申请人： Marshall J. Bell
发明人： Marshall J. Bell
IPC分类号： H03F345
CPC分类号： H03F3/45744 , H03F3/45192 , H03F2203/45248 , H03F2203/45264 , H03F2203/45352 , H03F2203/45512 , H03F2203/45676
摘要： A folded-cascode amplifier is arranged with a differential pair circuit, a current mirror circuit, and a cascode circuit. The differential pair is coupled to the current mirror circuit, while the cascode circuit is only coupled to one half of the current mirror circuit. A minimum number of transistors are employed such that overall speed is improved. An output stage with a compensation circuit may be coupled to an output of the cascode circuit. The cascode circuit is configured such that the compensation capacitor is driven with a current of approximately +/−2*I when slewing in the positive and negative directions.
摘要翻译：折叠共源共栅放大器配置有差分对电路，电流镜电路和共源共栅电路。差分对耦合到电流镜电路，而共源共栅电路仅耦合到电流镜电路的一半。采用最小数量的晶体管，使得总体速度得到改善。具有补偿电路的输出级可以耦合到共源共栅电路的输出端。共源共栅电路被配置成使得当在正向和负向旋转时，补偿电容器以大约+/- 2 * I的电流驱动。

7. 发明授权

US06359449B1 Single coil conductance measuring apparatus 失效
标题翻译：单线圈电导测量仪
公开(公告)号：US06359449B1
公开(公告)日：2002-03-19
申请号：US09343166
申请日：1999-06-29
申请人： William N. Reining , Marshall J. Bell
发明人： William N. Reining , Marshall J. Bell
IPC分类号： G01R2708
CPC分类号： G01R27/08
摘要： A conductance sensor uses a high impedance feedback oscillator to drive a single coil at the natural resonant frequency of the coil coupled to a measured material. The amplitude of the driving signal is also feedback controlled. The error signal of the amplitude control yields a measurement of resistance of the measured material. The combination of frequency adjustment and amplitude control eliminates non-resistance impedance effects and amplitude-dependent effects allowing high precision, high sensitivity measurement.
摘要翻译：电导传感器使用高阻抗反馈振荡器以耦合到测量材料的线圈的固有谐振频率驱动单个线圈。驱动信号的振幅也是反馈控制的。振幅控制的误差信号产生测量材料的电阻的测量。频率调节和幅度控制的组合消除了非电阻阻抗效应和幅度相关效应，从而实现高精度，高灵敏度测量。

8. 发明授权

US07906994B2 Fast common mode feedback control for differential driver 有权
标题翻译：差分驱动器的快速共模反馈控制
公开(公告)号：US07906994B2
公开(公告)日：2011-03-15
申请号：US12391414
申请日：2009-02-24
申请人： Marshall J. Bell
发明人： Marshall J. Bell
IPC分类号： H03K3/00
CPC分类号： H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/456 , H03F2200/78 , H03F2203/45008 , H03F2203/45074 , H03F2203/45292 , H03F2203/45418 , H03F2203/45424 , H03F2203/45631 , H04L25/0276
摘要： A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage.
摘要翻译：用于快速稳定输出缓冲器的系统和方法。差分驱动器电路具有用于接收差分输入信号并基于输入信号产生差分输出的放大器级。差分输出具有通常基于电源的一半值的对应的共模（CM）电压电平。共模反馈缓冲器（CMFB）级检测CM电压电平的变化，并且基于非常高的总线频率在非常快的建立时间内将CM电压电平恢复到其期望值。 CMFB阶段使用仅包含单个设备的拓扑。在一个实施例中，该单个器件是用作跨阻抗级的nmos晶体管。稳定性由CMFB级内的电路偏置级和分流电容提供。

9. 发明申请

US20100213985A1 FAST COMMON MODE FEEDBACK CONTROL FOR DIFFERENTIAL DRIVER 有权
标题翻译：用于差分驱动器的快速共同模式反馈控制
公开(公告)号：US20100213985A1
公开(公告)日：2010-08-26
申请号：US12391414
申请日：2009-02-24
申请人： Marshall J. Bell
发明人： Marshall J. Bell
IPC分类号： H03B1/00
CPC分类号： H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/456 , H03F2200/78 , H03F2203/45008 , H03F2203/45074 , H03F2203/45292 , H03F2203/45418 , H03F2203/45424 , H03F2203/45631 , H04L25/0276
摘要： A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage.
摘要翻译：用于快速稳定输出缓冲器的系统和方法。差分驱动器电路具有用于接收差分输入信号并基于输入信号产生差分输出的放大器级。差分输出具有通常基于电源的一半值的对应的共模（CM）电压电平。共模反馈缓冲器（CMFB）级检测CM电压电平的变化，并且基于非常高的总线频率在非常快的建立时间内将CM电压电平恢复到其期望值。 CMFB阶段使用仅包含单个设备的拓扑。在一个实施例中，该单个器件是用作跨阻抗级的nmos晶体管。稳定性由CMFB级内的电路偏置级和分流电容提供。

10. 发明授权

US07355577B1 Linear DAC in liquid crystal display column driver 有权
标题翻译：线性DAC在液晶显示列驱动
公开(公告)号：US07355577B1
公开(公告)日：2008-04-08
申请号：US10850973
申请日：2004-05-21
申请人： Marshall J. Bell , Richard I. McCartney
发明人： Marshall J. Bell , Richard I. McCartney
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3688 , G09G2310/027 , G09G2320/0276 , G09G2320/041 , G09G2320/0666
摘要： A method and circuit for providing analog voltages to an LCD panel based on digital voltages. A gamma curve defining a relationship between the applied voltage and a luminescence of the liquid crystals is implemented in a timing controller through a look-up table, an algorithm, and the like. The digital grey level voltages provided by the timing controller are converted to analog voltages by a linear digital-analog-converter (DAC) in each column driver. Implementation of the gamma curve in the timing controller and use of linear DAC allows accommodation of higher bit rate without significant die area increase. Furthermore, look-up table style implementation of the gamma curve allows for easy modification of the curve for temperature, color temperature, different color schemes, and the like.
摘要翻译：一种基于数字电压向LCD面板提供模拟电压的方法和电路。通过查找表，算法等在定时控制器中实现限定施加的电压和液晶的发光之间的关系的伽马曲线。由定时控制器提供的数字灰度级电压通过每列驱动器中的线性数模转换器（DAC）转换为模拟电压。在定时控制器中使用伽马曲线并使用线性DAC可以调节更高的比特率，而不会有明显的裸片面积增加。此外，伽马曲线的查找表样式实现允许容易地修改温度，色温，不同配色方案等的曲线。

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