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1. 发明授权

US10146434B1 FIFO systems and methods for providing access to a memory shared by multiple devices 有权
公开(公告)号：US10146434B1
公开(公告)日：2018-12-04
申请号：US15150931
申请日：2016-05-10
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Dror Bromberg , Roi Sherman
IPC分类号： G06F13/00 , G06F3/06 , H04L12/879 , H04L29/08 , G06F12/0871
摘要： A First-In-First-Out (FIFO) system and a method for providing access to a memory shared by a plurality of N clients are provided. The memory has a single memory space for holding a plurality of data storage arrays that are respectively configured to store data in a first-in-first-out manner for corresponding clients among the N clients. An arbiter is configured to receive memory access requests from two or more of the N clients to perform a FIFO operation, to push data into a corresponding storage array or to pop data from the corresponding storage array in response to the memory access request. The arbiter is configured to select a first at least one of the clients to perform a first FIFO operation in a first memory operation cycle and to select a second at least one of the clients to perform a second FIFO operation in a second memory operation cycle.

2. 发明授权

US09870319B1 Multibank queuing system 有权
公开(公告)号：US09870319B1
公开(公告)日：2018-01-16
申请号：US15090369
申请日：2016-04-04
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Sharon Ulman , Roi Sherman , Dror Bromberg , Carmi Arad
IPC分类号： H04L12/28 , H04L12/56 , G06F12/06 , G06F7/58 , G06F13/16 , H04L12/879
CPC分类号： G06F12/0623 , G06F7/582 , G06F12/0246 , G06F13/1647 , G06F13/1694 , G06F2212/2532 , G06F2212/261 , H04L49/90 , H04L49/901
摘要： Data items to be stored in a queue are received, where the queue is distributed among a plurality of memory banks. The data items are distributed among the plurality of memory banks, including selecting memory banks in which to store the data items based on pseudorandom numbers generated for the data items, where the pseudorandom numbers are generated using a first pseudorandom number generator initialized with a first seed. Subsequently the data items are retrieved from the plurality of memory banks, including selecting memory banks from which to retrieve the data items based on the pseudorandom numbers regenerated for the data items, where the pseudorandom numbers are regenerated using a second pseudorandom number generator initialized with the first seed.

3. 发明授权

US10021035B1 Queuing methods and apparatus in a network device 有权
公开(公告)号：US10021035B1
公开(公告)日：2018-07-10
申请号：US15489007
申请日：2017-04-17
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Gal Malchi , Dror Bromberg
IPC分类号： H04L12/861 , H04L12/865 , H04L12/863 , H04L12/883 , H04L12/851 , H04W28/06 , H04L12/801
CPC分类号： H04L47/6275 , H04L47/10 , H04L47/24 , H04L47/6225 , H04L47/6295 , H04L49/9015 , H04L49/9047 , H04W28/06
摘要： A plurality of physical queues, in a memory of a network device, are logically coupled to define a logical queue. Packets are received by the network device, and respective data units associated with the packets are distributed to the plurality of physical queues for storage according to a predetermined scheme i) to alternate among the plurality of physical queues, and ii) to maintain an order of data units stored in the logical queue. The data units are retrieved from the plurality of physical queues according to the predetermined scheme i) to alternate among the plurality of physical queues, and ii) to maintain the order of the data units.

4. 发明授权

US09112708B1 Processing multicast packets in a network device 有权
标题翻译：处理网络设备中的组播数据包
公开(公告)号：US09112708B1
公开(公告)日：2015-08-18
申请号：US13752042
申请日：2013-01-28
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Carmi Arad , Gil Levy , Lior Valency , Amir Roitshtein , Sharon Ulman , Dror Bromberg
IPC分类号： H04L12/56 , H04L12/18
CPC分类号： H04L12/18 , H04L49/201 , H04L49/901
摘要： A network switch device comprises a packet processor configured to: write, to a memory, at least a payload of a multicast packet received via one of a plurality of ports, determine that a plurality of instances of the multicast packet are to be transmitted, generate, using an original header of the multicast packet, one or more additional headers, write, to the memory, a plurality of headers including (i) the original header, and (ii) the one or more additional headers in the memory, link each header in the plurality of headers stored in the memory to a location of the payload in the memory, and transmit a plurality of instances of the multicast packet via one or more ports including, for each instance of the multicast packet, reading (i) a respective one of the headers from the memory and (ii) the payload from the location in the memory.
摘要翻译：一种网络交换机设备包括分组处理器，其被配置为：向存储器写入至少通过多个端口之一接收到的多播分组的有效载荷，确定要发送多个组播分组的多个实例，生成使用多播分组的原始报头，一个或多个附加报头，向存储器写入多个报头，其包括（i）原始报头，以及（ii）存储器中的一个或多个附加报头，将每个将存储在存储器中的多个报头中的报头发送到存储器中的有效载荷的位置，并且经由一个或多个端口发送多个多播实例，包括对于多播分组的每个实例，读取（i）相应的一个来自存储器的头部和（ii）从存储器中的位置的有效载荷。

5. 发明授权

US09628398B1 Queuing methods and apparatus in a network device 有权
公开(公告)号：US09628398B1
公开(公告)日：2017-04-18
申请号：US13781125
申请日：2013-02-28
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Gal Malchi , Dror Bromberg
IPC分类号： H04L12/865
CPC分类号： H04L47/6275 , H04L47/10 , H04L47/24 , H04L47/6225 , H04L47/6295 , H04L49/9015 , H04L49/9047 , H04W28/06
摘要： In a method for queuing data units in a network device, a plurality of physical queues corresponding to a port of the network device are defined in a memory of the network device. Respective subsets of the plurality of physical queues are logically coupled to define a plurality of logical queues that are respectively formed of logically coupled physical queues. The logical queues correspond to respective data flows of the port. A data unit belonging to a data flow is received. A logical queue for storing the data unit is selected, based on the data flow of the data unit, from the plurality of logical queues The A physical queue for storing the data unit is then selected from the subset of physical queues that corresponds to the selected logical queue. The data unit is stored in the selected physical queue.

6. 发明授权

US09306876B1 Multibank egress queuing system in a network device 有权
标题翻译：网络设备中的多单元出口排队系统
公开(公告)号：US09306876B1
公开(公告)日：2016-04-05
申请号：US14242321
申请日：2014-04-01
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Sharon Ulman , Roi Sherman , Dror Bromberg , Carmi Arad
IPC分类号： H04L12/28 , H04L12/56 , H04L12/861 , G06F12/02 , H04L12/879
CPC分类号： G06F12/0623 , G06F7/582 , G06F12/0246 , G06F13/1647 , G06F13/1694 , G06F2212/2532 , G06F2212/261 , H04L49/90 , H04L49/901
摘要： In a method of managing queues in an egress queuing system in a network device, a plurality of packets to be stored in a first egress queue are received. The first egress queue is distributed among a plurality of memory banks. The packets are distributed among the plurality of memory banks. Memory banks in which to store the packets are selected based on pseudorandom numbers generated for the packets. The pseudorandom numbers are generated using a first pseudorandom number generator initialized with a first seed. Subsequently, the packets are retrieved from the plurality of memory banks. Memory banks from which to retrieve the packets are selected based on pseudorandom numbers regenerated for the packets. The pseudorandom numbers are regenerated using a second pseudorandom number generator initialized with the first seed.
摘要翻译：在网络设备的出口排队系统中管理队列的方法中，接收要存储在第一出口队列中的多个分组。第一出口队列分布在多个存储体之间。分组分布在多个存储体之间。基于为数据包生成的伪随机数，选择存储分组的存储体。伪随机数是使用第一种子初始化的第一个伪随机数生成器生成的。随后，从多个存储体中检索分组。基于为数据包重新生成的伪随机数，选择从中检索数据包的存储器组。使用用第一种子初始化的第二伪随机数生成器来再生伪随机数。

7. 发明授权

US10177997B1 Method and apparatus for packet and byte counting 有权
公开(公告)号：US10177997B1
公开(公告)日：2019-01-08
申请号：US14933466
申请日：2015-11-05
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Dror Bromberg , Carmi Arad
IPC分类号： H04L12/28 , H04L12/26 , H04L12/24
摘要： A network device and a method for maintaining a count of network events in a network device are provided. A first memory is configured as a first counter, where the first counter is configured to store a least significant bit (LSb) portion of a count value. A second memory is configured as a second counter, where the second counter is configured to store a most significant bit (MSb) portion of the count value. Update circuitry is configured to (i) selectively increment or decrement the LSb portion of the count value stored in the first memory upon occurrence of an event, and (ii) selectively increment or decrement the MSb portion of the count value stored in the second memory upon occurrence of a wrap-around event in the first memory.

8. 发明授权

US10089018B2 Multi-bank memory with multiple read ports and multiple write ports per cycle 有权
公开(公告)号：US10089018B2
公开(公告)日：2018-10-02
申请号：US15130980
申请日：2016-04-17
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Dror Bromberg , Roi Sherman , Rami Zemach
IPC分类号： G06F12/00 , G06F3/06 , G06F12/06
摘要： A method for data storage includes receiving one or more read commands and one or more write commands, for execution in a same clock cycle in a memory array that comprises multiple single-port memory banks divided into groups. The write commands provide data for storage but do not specify storage locations in which the data is to be stored. One or more of the groups, which are not accessed by the read commands in the same clock cycle, are selected. Available storage locations are chosen for the write commands in the single-port memory banks of the selected one or more groups. During the same clock cycle, the data provided in the write commands is stored in the chosen storage locations, and the data requested by the read commands is retrieved. Execution of the write commands is acknowledged by reporting the chosen storage locations.

9. 发明申请

US20160328158A1 MULTI-BANK MEMORY WITH MULTIPLE READ PORTS AND MULTIPLE WRITE PORTS PER CYCLE 审中-公开
标题翻译：具有多个读取端口和多个写入端口的多存储存储器
公开(公告)号：US20160328158A1
公开(公告)日：2016-11-10
申请号：US15130980
申请日：2016-04-17
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Dror Bromberg , Roi Sherman , Rami Zemach
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0611 , G06F3/0619 , G06F3/0656 , G06F3/0659 , G06F3/067 , G06F12/06 , G06F12/0607 , G06F2212/1024 , Y02D10/13
摘要： A method for data storage includes receiving one or more read commands and one or more write commands, for execution in a same clock cycle in a memory array that comprises multiple single-port memory banks divided into groups. The write commands provide data for storage but do not specify storage locations in which the data is to be stored. One or more of the groups, which are not accessed by the read commands in the same clock cycle, are selected. Available storage locations are chosen for the write commands in the single-port memory banks of the selected one or more groups. During the same clock cycle, the data provided in the write commands is stored in the chosen storage locations, and the data requested by the read commands is retrieved. Execution of the write commands is acknowledged by reporting the chosen storage locations.
摘要翻译：一种用于数据存储的方法包括接收一个或多个读取命令和一个或多个写入命令，用于在包括分成组的多个单端口存储器组的存储器阵列中以相同的时钟周期执行。写命令提供用于存储的数据，但不指定要存储数据的存储位置。选择在相同时钟周期中不被读取命令访问的一个或多个组。为所选一个或多个组的单端口存储体中的写入命令选择可用的存储位置。在相同的时钟周期内，写入命令中提供的数据被存储在所选择的存储位置，并且检索读取命令请求的数据。通过报告所选择的存储位置来确认写命令的执行。

10. 发明授权

US09158715B1 Multi-input memory command prioritization 有权
标题翻译：多输入存储器命令优先级
公开(公告)号：US09158715B1
公开(公告)日：2015-10-13
申请号：US13773930
申请日：2013-02-22
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Dror Bromberg
IPC分类号： G06F12/00 , G06F13/16 , G06F12/08
CPC分类号： G06F13/1689 , G06F12/0844 , G06F12/0853 , G06F13/161 , G06F13/1631
摘要： Described herein are memory apparatuses, and methods of operating the same, that have a memory array module configured, in a given clock cycle, to either receive a first command to write to a first memory location having a first address, or receive a second command to read from a second memory location having a second address. A comparison circuit of the memory apparatus is configured to compare the first address to the second address. The memory apparatus also includes an output circuit configured to output data stored in the memory array module at the second memory location based at least on the first address and second address being different. The output circuit is also configured to output data received from a write data input, bypassing the memory array module, when the first address and the second address are the same.
摘要翻译：这里描述的是具有在给定时钟周期中配置的存储器阵列模块的存储器装置及其操作方法，以便接收第一命令以写入具有第一地址的第一存储器位置，或接收第二命令从具有第二地址的第二存储器位置读取。存储装置的比较电路被配置为将第一地址与第二地址进行比较。存储装置还包括输出电路，其被配置为至少基于第一地址和第二地址不同地在第二存储器位置输出存储在存储器阵列模块中的数据。输出电路还被配置为当第一地址和第二地址相同时，输出绕过存储器阵列模块的写数据输入接收的数据。

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