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1. 发明授权

US11036807B2 Metadata generation at the storage edge 有权
公开(公告)号：US11036807B2
公开(公告)日：2021-06-15
申请号：US16262975
申请日：2019-01-31
申请人： Marvell World Trade Ltd.
发明人： Noam Mizrahi
IPC分类号： G06F16/907 , G06F16/901 , G06F16/9038 , G06F16/9035 , G06F16/783 , G06F16/387 , G06F16/683 , G06F16/383 , G06F3/06 , G06N3/08 , G06F12/1045 , G06F15/173 , H04L12/879 , H04L29/08
摘要： A controller, for use in a storage device of a data processing system, includes a host interface, a memory interface and one or more processors. The host interface is configured to communicate over a computer network with one or more remote hosts of a data processing system. The memory interface is configured to communicate locally with a non-volatile memory of the storage device. The one or more processors are configured to manage local storage or retrieval of media objects at the non-volatile memory, and to selectively compute metadata that defines content characteristics of media objects that are stored, or that are to be stored, in the non-volatile memory.

2. 发明申请

US20200042548A1 Metadata generation for multiple object types 审中-公开
公开(公告)号：US20200042548A1
公开(公告)日：2020-02-06
申请号：US16262971
申请日：2019-01-31
申请人： Marvell World Trade Ltd.
发明人： Noam Mizrahi
IPC分类号： G06F16/383 , G06F16/387 , G06F3/06 , G06F16/683 , G06F16/783 , G06N3/08
摘要： Metadata computation apparatus includes a host interface, a storage interface and one or more processors. The host interface is configured to communicate over a computer network with one or more remote hosts. The storage interface is configured to communicate with one or more non-volatile memories of one or more storage devices. The processors are configured to manage local storage or retrieval of media objects in the non-volatile memories, to compute metadata for a plurality of media objects that are stored, or are en-route for storage, on the storage devices, wherein the media objects are of multiple media types, wherein the computed metadata tags a target feature in the media objects of at least two different media types among the multiple media types, and to store, in the non-volatile memories, the metadata tagging the target feature found in the at least two different media types, for use by the hosts.

3. 发明申请

US20170180156A1 INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM 审中-公开
公开(公告)号：US20170180156A1
公开(公告)日：2017-06-22
申请号：US15453262
申请日：2017-03-08
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Shaul Chapman , Erez Amit , Noam Mizrahi , Moshe Raz , Husam Khshaiboun , Amit Shmilovich , Sujat Jamil , Frank O'Bleness
IPC分类号： H04L12/46 , G06F12/0811 , G06F12/0815
CPC分类号： H04L12/4637 , G06F12/0811 , G06F12/0813 , G06F12/0815 , G06F13/1657 , G06F15/17375 , G06F2212/283 , G06F2212/621 , H04L2012/421
摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

4. 发明授权

US09298628B2 Shared op-symmetric update-sensitive variables 有权
公开(公告)号：US09298628B2
公开(公告)日：2016-03-29
申请号：US14154698
申请日：2014-01-14
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Noam Mizrahi
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804
摘要： Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.

5. 发明申请

US20140201470A1 SHARED OP-SYMMETRIC UPDATE-SENSITIVE VARIABLES 审中-公开
标题翻译：共享对称更新敏感变量
公开(公告)号：US20140201470A1
公开(公告)日：2014-07-17
申请号：US14154698
申请日：2014-01-14
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Noam Mizrahi
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804
摘要： Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.
摘要翻译：实施例包括多处理器系统，包括多核处理器系统，以及用于操作相同的处理器系统的方法，其中至少一个处理器或处理器核心被配置为接收指示至少一个处理器核心以读取相关值的指令与一个内存地址。响应于接收到指令并且在执行指令之前，至少一个处理器或处理器核心使多个相互通信的耦合在一起的处理器核心中的一个提供多个本地存储的值，该多个本地存储的值被分别存储在相应的处理器内核并与存储器地址相关联。

6. 发明授权

US09298627B2 Shared op-symmetric update-sensitive variables 有权
标题翻译：共享的对称更新敏感变量
公开(公告)号：US09298627B2
公开(公告)日：2016-03-29
申请号：US14153526
申请日：2014-01-13
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Noam Mizrahi
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804
摘要： Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.
摘要翻译：实施例包括多处理器系统，包括多核处理器系统，以及用于操作相同的处理器系统的方法，其中至少一个处理器或处理器核被配置为接收指示至少一个处理器核心的指令以读取相关值与一个内存地址。响应于接收到指令并且在执行指令之前，至少一个处理器或处理器核心使多个相互通信的耦合在一起的处理器核心中的一个提供多个本地存储的值，该多个本地存储的值被分别存储在相应的处理器内核并与存储器地址相关联。

7. 发明申请

US20200042549A1 Metadata Generation at the Storage Edge 审中-公开
公开(公告)号：US20200042549A1
公开(公告)日：2020-02-06
申请号：US16262975
申请日：2019-01-31
申请人： Marvell World Trade Ltd.
发明人： Noam Mizrahi
IPC分类号： G06F16/383 , G06F16/387 , G06F16/783 , G06F3/06 , G06N3/08
摘要： A controller, for use in a storage device of a data processing system, includes a host interface, a memory interface and one or more processors. The host interface is configured to communicate over a computer network with one or more remote hosts of a data processing system. The memory interface is configured to communicate locally with a non-volatile memory of the storage device. The one or more processors are configured to manage local storage or retrieval of media objects at the non-volatile memory, and to selectively compute metadata that defines content characteristics of media objects that are stored, or that are to be stored, in the non-volatile memory.

8. 发明授权

US10230542B2 Interconnected ring network in a multi-processor system 有权
公开(公告)号：US10230542B2
公开(公告)日：2019-03-12
申请号：US15453262
申请日：2017-03-08
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Shaul Chapman , Erez Amit , Noam Mizrahi , Moshe Raz , Husam Khshaiboun , Amit Shmilovich , Sujat Jamil , Frank O'Bleness
IPC分类号： H04L12/46 , G06F12/0813 , G06F12/0815 , G06F13/16 , G06F15/173 , G06F12/0811 , H04L12/42
摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

9. 发明申请

US20170286363A1 METHODS AND SYSTEMS FOR ACCESSING HOST MEMORY THROUGH NON-VOLATILE MEMORY OVER FABRIC BRIDGING WITH DIRECT TARGET ACCESS 审中-公开
公开(公告)号：US20170286363A1
公开(公告)日：2017-10-05
申请号：US15479005
申请日：2017-04-04
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Scott Furey , Dimitry Melts , Noam Mizrahi
IPC分类号： G06F15/173 , G06F13/28 , G06F3/06 , H04L29/06
摘要： Embodiments described herein provide a method for accessing a host memory through non-volatile memory over fabric bridging with direct target access. A first memory access command encapsulated in a first network packet is received at a memory interface unit and from a remote direct memory access (RDMA) interface and via a network fabric. The first memory access command is compliant with a first non-volatile memory interface protocol and the first network packet is compliant with a second non-volatile memory interface protocol. The first network packet is unwrapped to obtain the first memory access command. The first memory access command is stored in a work queue using address bits of the work queue as a pre-set index of the first memory access command. The first memory access command is sent from the work queue based on the pre-set index to activate a first target storage device.

10. 发明申请

US20140201326A1 INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM 审中-公开
公开(公告)号：US20140201326A1
公开(公告)日：2014-07-17
申请号：US14155773
申请日：2014-01-15
申请人： Marvell World Trade Ltd.
发明人： Eitan Joshua , Shaul Chapman , Erez Amit , Noam Mizrahi , Moshe Raz , Husam Khshaiboun , Amit Shmilovich , Sujat Jamil , Frank O'Bleness
IPC分类号： H04L12/46
CPC分类号： H04L12/4637 , G06F12/0811 , G06F12/0813 , G06F12/0815 , G06F13/1657 , G06F15/17375 , G06F2212/283 , G06F2212/621 , H04L2012/421
摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

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