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1. 发明授权

US07253096B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US07253096B2
公开(公告)日：2007-08-07
申请号：US11289915
申请日：2005-11-30
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

2. 发明申请

US20050233535A1 Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same 失效
公开(公告)号：US20050233535A1
公开(公告)日：2005-10-20
申请号：US11150894
申请日：2005-06-13
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
IPC分类号： H01L29/737 , H01L21/331 , H01L21/8222 , H01L29/10 , H01L29/732 , H01L21/328 , H01L29/70
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.

3. 发明授权

US06858485B2 Method for creation of a very narrow emitter feature 失效
标题翻译：用于创建非常窄的发射器特征的方法
公开(公告)号：US06858485B2
公开(公告)日：2005-02-22
申请号：US10249780
申请日：2003-05-07
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L21/8238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面上的掺杂发射极。在收集器上方的本征基底层上形成蚀刻停止介电层。在蚀刻停止介电层和本征基极层上形成导电材料的基底接触层。在基底接触层上形成第二介电层。通过介电层和基底接触层蚀刻宽窗口，停止在蚀刻停止介电层处的窗口的蚀刻。形成一个岛屿或一个半岛，缩小广阔的窗户，在宽阔的窗口内至少留出一个狭窄的窗户。在宽窗口或狭窄的窗户中形成侧壁间隔物。用掺杂多晶硅填充窗口以形成外部发射极。在本征基表面的外部发射极之下形成发射体。

4. 发明授权

US07732292B2 Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide 失效
标题翻译：双向晶体管，具有自对准逆向外基极植入轮廓和自对准硅化物
公开(公告)号：US07732292B2
公开(公告)日：2010-06-08
申请号：US11838948
申请日：2007-08-15
申请人： Marwan H. Khater , Francois Pagette
发明人： Marwan H. Khater , Francois Pagette
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66272 , H01L29/732
摘要： Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.
摘要翻译：公开了一种在集成电路结构中形成晶体管的方法，其通过在基板中形成集电体和在集电极之上形成本征基极而开始。然后，本发明在基底上方的发光体的下部的内部基底上形成发射极基座。在实际形成发射极或者相关的间隔物之前，本发明在不受发射极基座保护的衬底的区域中形成非本征基极。之后，本发明去除发射器基座并最终形成发射器底座所在的发射极。

5. 发明授权

US07611954B2 Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same 失效
标题翻译：双极晶体管自对准具有凸起的外在基极延伸及其形成方法
公开(公告)号：US07611954B2
公开(公告)日：2009-11-03
申请号：US11150894
申请日：2005-06-13
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
IPC分类号： H01L21/8222
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.
摘要翻译：公开了具有包括外部区域和不同掺杂浓度的内部区域的升高的外部基极的自对准双极晶体管结构和制造晶体管的方法。更具体地说，外部碱基与发射体的自对准是通过在两个区域中形成外部碱基来实现的。首先，提供具有第一掺杂浓度的硅或多晶硅的第一材料以形成外部外在基极区域。然后通过光刻形成在第一材料层中的第一开口，在该第一材料层内形成有虚拟发射极基座，这导致在第一开口的侧壁和虚拟基座之间形成沟槽。然后在沟槽的内部提供第二掺杂浓度的第二材料，形成不同的内部非本征基本延伸区域，以将凸起的本征基底边缘自对准到虚拟基座边缘。由于发射极形成在存在虚拟基座的位置，所以外部基极也与发射极自对准。形成内部非本征基极延伸区域的硅或多晶硅也可以在具有选择性或非选择性外延的沟槽中生长。

6. 发明授权

US07087940B2 Structure and method of forming bipolar transistor having a self-aligned raised extrinsic base using self-aligned etch stop layer 有权
标题翻译：使用自对准蚀刻停止层形成具有自对准凸起外部基极的双极晶体管的结构和方法
公开(公告)号：US07087940B2
公开(公告)日：2006-08-08
申请号：US10709220
申请日：2004-04-22
申请人： Marwan H. Khater , Francois Pagette
发明人： Marwan H. Khater , Francois Pagette
IPC分类号： H01L31/072 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/7378
摘要： A bipolar transistor structure and method of making the bipolar transistor are provided. The bipolar transistor includes a collector region, an intrinsic base layer overlying the collector region, and an emitter overlying the intrinsic base layer. An opened etch stop layer includes a layer of dielectric material overlying the intrinsic base, the opened etch stop layer self-aligned to the emitter. The bipolar transistor further includes a raised extrinsic base self-aligned to the emitter, the raised extrinsic base overlying the intrinsic base layer.
摘要翻译：提供双极晶体管结构和制造双极晶体管的方法。双极晶体管包括集电极区域，覆盖集电极区域的本征基极层和覆盖本征基极层的发射极。开放的蚀刻停止层包括覆盖本征基底的介电材料层，该开放的蚀刻停止层与发射极自对准。双极晶体管还包括与发射极自对准的升高的外部基极，凸起的外在基极覆盖本征基极层。

7. 发明授权

US06960820B2 Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same 有权
标题翻译：双极晶体管自对准具有凸起的外在基极延伸及其形成方法
公开(公告)号：US06960820B2
公开(公告)日：2005-11-01
申请号：US10604212
申请日：2003-07-01
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
IPC分类号： H01L29/737 , H01L21/331 , H01L21/8222 , H01L29/10 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.
摘要翻译：公开了具有包括外部区域和不同掺杂浓度的内部区域的升高的外部基极的自对准双极晶体管结构和制造晶体管的方法。更具体地说，外部碱基与发射体的自对准是通过在两个区域中形成外部碱基来实现的。首先，提供具有第一掺杂浓度的硅或多晶硅的第一材料以形成外部外在基极区域。然后通过光刻形成在第一材料层中的第一开口，在该第一材料层内形成有虚拟发射极基座，这导致在第一开口的侧壁和虚拟基座之间形成沟槽。然后在沟槽内部设置第二掺杂浓度的第二材料，形成不同的内部非本征基本延伸区域，以将凸起的本征基底边缘自对准到虚拟基座边缘。由于发射极形成在存在虚拟基座的位置，所以外部基极也与发射极自对准。形成内部非本征基极延伸区域的硅或多晶硅也可以在具有选择性或非选择性外延的沟槽中生长。

8. 发明授权

US07180157B2 Bipolar transistor with a very narrow emitter feature 失效
标题翻译：双极晶体管具有非常窄的发射极特性
公开(公告)号：US07180157B2
公开(公告)日：2007-02-20
申请号：US10978775
申请日：2004-11-01
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。电介质层覆盖在基底接触层上。宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。

9. 发明授权

US07002221B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 有权
公开(公告)号：US07002221B2
公开(公告)日：2006-02-21
申请号：US10604988
申请日：2003-08-29
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

10. 发明授权

US08716807B2 Fabrication of devices having different interfacial oxide thickness via lateral oxidation 有权
标题翻译：通过侧面氧化制备具有不同界面氧化物厚度的器件
公开(公告)号：US08716807B2
公开(公告)日：2014-05-06
申请号：US13571521
申请日：2012-08-10
申请人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
发明人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
IPC分类号： H01L21/70
CPC分类号： H01L21/823468 , H01L21/28176 , H01L21/28247 , H01L21/823462 , H01L21/823857 , H01L21/823864 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/78
摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.
摘要翻译：半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

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