专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140061773A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140061773A1
公开(公告)日：2014-03-06
申请号：US13728311
申请日：2012-12-27
申请人： Masaaki HIGUCHI , Masaru Kito
发明人： Masaaki HIGUCHI , Masaru Kito
IPC分类号： H01L29/792
CPC分类号： H01L27/105 , H01L21/8229 , H01L21/8239 , H01L27/11 , H01L27/112 , H01L27/115 , H01L27/11582 , H01L29/685 , H01L29/792
摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of insulative separating films, a channel body, and a memory film. The stacked body includes a plurality of electrode layers and a plurality of insulating layers. The plurality of insulative separating films separates the stacked body into a plurality. The channel body extends in the stacking direction between the plurality of insulative separating films. A width of the electrode layer of a lower layer side between the insulative separating film and the memory film is greater than a width of the electrode layer of an upper layer side between the insulative separating film and the memory film. An electrical resistivity of the electrode layer is higher for the electrode layer of the lower layer side having the greater width than for the electrode layer of the upper layer side having the lesser width.
摘要翻译：根据一个实施例，半导体存储器件包括衬底，层叠体，多个绝缘分离膜，通道体和存储膜。层叠体包括多个电极层和多个绝缘层。多个绝缘分离膜将堆叠体分离成多个。通道体在层叠方向上在多个绝缘分离膜之间延伸。绝缘分离膜和记忆膜之间的下层侧的电极层的宽度大于绝缘分离膜和记忆膜之间的上层侧的电极层的宽度。对于具有比具有较小宽度的上层侧的电极层的宽度大的下层侧的电极层，电极层的电阻率较高。

2. 发明申请

US20120235220A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120235220A1
公开(公告)日：2012-09-20
申请号：US13234406
申请日：2011-09-16
申请人： Katsuyuki SEKINE , Masaaki HIGUCHI
发明人： Katsuyuki SEKINE , Masaaki HIGUCHI
IPC分类号： H01L29/792
CPC分类号： H01L27/11582
摘要： According to one embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a charge storage film, a second insulating film and a channel body. The stacked body includes a plurality of electrode layers and insulating layers which are alternately stacked above the substrate. The first insulating film is provided on a side wall of a hole which is formed through the stacked body. The charge storage film is provided on an inner side of the first insulating film. The charge storage film includes a protrusion part which protrudes toward the electrode layer with facing the electrode layer and has a film thickness thicker than a film thickness of a part other than the protrusion part. The second insulating film is provided on an inner side of the charge storage film. The channel body is provided on an inner side of the second insulating film.
摘要翻译：根据一个实施例，半导体器件包括衬底，层叠体，第一绝缘膜，电荷存储膜，第二绝缘膜和通道体。层叠体包括交替层叠在基板的上方的多个电极层和绝缘层。第一绝缘膜设置在通过层叠体形成的孔的侧壁上。电荷存储膜设置在第一绝缘膜的内侧。电荷存储膜包括突出部分，其朝着电极层朝向电极层突出，并且具有比除了突出部分之外的部分的膜厚度厚的膜厚度。第二绝缘膜设置在电荷存储膜的内侧。通道体设置在第二绝缘膜的内侧。

3. 发明申请

US20110049612A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110049612A1
公开(公告)日：2011-03-03
申请号：US12855212
申请日：2010-08-12
申请人： Masaaki HIGUCHI , Yoshio Ozawa , Katsuyuki Sekine , Ryota Fujitsuka
发明人： Masaaki HIGUCHI , Yoshio Ozawa , Katsuyuki Sekine , Ryota Fujitsuka
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/66833
摘要： According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
摘要翻译：根据一个实施例，一种非易失性半导体存储器件，包括具有主表面的半导体层，形成在半导体层的主表面上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在第一绝缘层上的第二绝缘层电荷存储层和形成在第二绝缘层上的控制栅电极。至少一个通过散射减少电子能量的非弹性散射膜被包含在电荷存储层和第二绝缘层中的至少一个中。

4. 发明申请

US20110193153A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110193153A1
公开(公告)日：2011-08-11
申请号：US13023025
申请日：2011-02-08
申请人： Masaaki HIGUCHI , Yoshio Ozawa
发明人： Masaaki HIGUCHI , Yoshio Ozawa
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a semiconductor pillar and a charge storage layer. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The semiconductor pillar is buried in the stacked body, and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode films and the semiconductor pillar. The electrode films are divided into a plurality of control gate electrodes. Each of the plurality of control gate electrodes faces the semiconductor pillar and sandwiches the charge storage layer with the semiconductor pillar.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括堆叠体，半导体柱和电荷存储层。层叠体包括交替层叠有多个电极膜的多个绝缘膜。半导体柱被埋置在层叠体中，并且在绝缘膜和电极膜的层叠方向上延伸。电荷存储层设置在电极膜和半导体柱之间。电极膜被分成多个控制栅电极。多个控制栅极电极中的每一个面对半导体柱并且用半导体柱夹着电荷存储层。

5. 发明申请

US20130228853A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20130228853A1
公开(公告)日：2013-09-05
申请号：US13601156
申请日：2012-08-31
申请人： Masaaki HIGUCHI , Atsushi Fukumoto
发明人： Masaaki HIGUCHI , Atsushi Fukumoto
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7827 , H01L21/28008 , H01L27/11578 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes: a substrate; a stacked body including a plurality of electrode layers and a plurality of insulating layers, both of them being alternately stacked on the substrate; a cap film provided in contact with the electrode layer within a hole formed to penetrate the stacked body; an insulating film provided on a side wall of the cap film and including a charge accumulation film; and a channel body provided on a side wall of the insulating film. The cap film includes a protrusion portion protruding toward the insulating film. In the cap film, a film thickness of a portion where the protrusion portion is provided in a direction in which the protrusion portion protrudes is larger than a film thickness of the other portions where the protrusion portion is not provided.
摘要翻译：根据一个实施例，半导体存储器件包括：衬底; 包括多个电极层和多个绝缘层的堆叠体，它们都交替堆叠在基板上; 在形成为穿透所述层叠体的孔内与所述电极层接触地设置的盖膜; 设置在所述盖膜的侧壁上并具有电荷蓄积膜的绝缘膜; 以及设置在绝缘膜的侧壁上的通道体。盖膜包括朝向绝缘膜突出的突出部。在盖膜中，突出部在突起部突出的方向上设置的部分的膜厚大于不设置突起部的其他部分的膜厚。

6. 发明申请

US20130056814A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130056814A1
公开(公告)日：2013-03-07
申请号：US13415057
申请日：2012-03-08
申请人： Masaaki HIGUCHI
发明人： Masaaki HIGUCHI
IPC分类号： H01L29/78
CPC分类号： H01L27/11582 , H01L27/1157
摘要： According to one embodiment, a semiconductor memory device includes a substrate, a first stacked body, a second stacked body, a memory film, a gate insulating film, and a channel body. The first stacked body has a plurality of electrode layers and a plurality of first insulating layers. The second stacked body has a selector gate and a second insulating layer. The memory film is provided on a sidewall of a first hole. The gate insulating film is provided on a sidewall of a second hole. The channel body is provided on an inner side of the memory film and on an inner side of the gate insulating film. A step part is provided between a side face of the selector gate and the second insulating layer. A region positioned near a top end of the selector gate of the channel body is silicided.
摘要翻译：根据一个实施例，半导体存储器件包括衬底，第一层叠体，第二层叠体，存储膜，栅极绝缘膜和沟道体。第一层叠体具有多个电极层和多个第一绝缘层。第二层叠体具有选择栅和第二绝缘层。记忆膜设置在第一孔的侧壁上。栅极绝缘膜设置在第二孔的侧壁上。通道体设置在存储膜的内侧和栅极绝缘膜的内侧。在选择栅极的侧面和第二绝缘层之间设置台阶部。位于通道主体的选择器门的顶端附近的区域被硅化。

7. 发明申请

US20100237402A1 SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有三维方向记忆细胞的半导体存储器件及其制造方法
公开(公告)号：US20100237402A1
公开(公告)日：2010-09-23
申请号：US12726952
申请日：2010-03-18
申请人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
摘要翻译：第一选择晶体管形成在半导体衬底上。存储单元晶体管堆叠在第一选择晶体管上并串联连接。在存储单元晶体管上形成第二选择晶体管。存储单元晶体管包括从第一选择晶体管朝向第二选择晶体管的直径增加的锥形半导体柱，形成在半导体柱的侧表面上的隧道电介质膜，形成在半导体柱的侧表面上的电荷存储层隧道电介质膜，并且其从第一选择晶体管侧朝向第二选择晶体管侧的电荷陷阱密度增加，形成在电荷存储层的侧表面上的块状电介质膜和形成在电荷存储层的侧表面上的导体膜该块介质膜并用作栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式