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    • 4. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08547723B2
    • 2013-10-01
    • US13398418
    • 2012-02-16
    • Shinji TanakaMakoto YabuuchiYuta Yoshida
    • Shinji TanakaMakoto YabuuchiYuta Yoshida
    • G11C8/08
    • G11C11/419G11C5/06G11C5/063G11C7/08G11C7/227G11C8/08G11C8/10G11C11/415G11C11/418
    • A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    • 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如,半导体器件设置有与适当的位线相对布置的虚拟位线,以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管,其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线,并且对应于负载电容,建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时,采用虚拟位线信号。
    • 6. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120224405A1
    • 2012-09-06
    • US13398418
    • 2012-02-16
    • Shinji TANAKAMakoto YabuuchiYuta Yoshida
    • Shinji TANAKAMakoto YabuuchiYuta Yoshida
    • G11C5/06
    • G11C11/419G11C5/06G11C5/063G11C7/08G11C7/227G11C8/08G11C8/10G11C11/415G11C11/418
    • A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    • 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如,半导体器件设置有与适当的位线相对布置的虚拟位线,以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管,其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线,并且对应于负载电容,建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时,采用虚拟位线信号。
    • 9. 发明授权
    • Optical information recording/reproducing optical system and optical information recording/reproducing apparatus
    • 光信息记录/再现光学系统和光信息记录/重放装置
    • US08339925B2
    • 2012-12-25
    • US12893382
    • 2010-09-29
    • Satoshi InoueYuta YoshidaNaoto HashimotoSuguru Takishima
    • Satoshi InoueYuta YoshidaNaoto HashimotoSuguru Takishima
    • G11B7/00
    • G11B7/1374G02B13/16G11B7/1376
    • An optical information recording/reproducing optical system, comprising a light source; an optical element converting a laser beam into a substantially collimated beam; and an objective lens, wherein a wavelength λ (unit: nm) of the laser beam falls within a range of 400 115° C., each of optical surfaces is configured not to have an optical thin film which contains at least one of or elements of titanium, tantalum, hafnium, zirconium, niobium, molybdenum and chromium, each of optical surfaces of the optical element is provided with an antireflection film made of one of or a mixture of at least two of silicon oxide, aluminum oxide, aluminum fluoride and magnesium fluoride, and a following condition is satisfied ∏ i = 1 n - 1 ⁢ ( 1 - R ( BL ) ⁢ i 100 ) - ∏ i = 1 n - 1 ⁢ ( 1 - R ( UV ) ⁢ i 100 ) > 0.05 .
    • 一种光信息记录/再现光学系统,包括光源; 将激光束转换成基本上准直的光束的光学元件; 和物镜,其中激光束的波长λ(单位:nm)落在400 <λ<410的范围内,光学元件和物镜由相同的树脂材料或具有玻璃化转变的不同树脂材料制成 Tg> 115℃的温度下,每个光学表面被配置为不具有包含钛,钽,铪,锆,铌,钼和铬中的至少一种或元素的光学薄膜,每个光学表面 光学元件设置有由氧化硅,氧化铝,氟化铝和氟化镁中的至少两种中的一种或其混合物制成的抗反射膜,满足以下条件Πi = 1 n-1(1- R(BL)i 100) - Πi = 1 n - 1(1-R(UV)i 100)> 0.05。
    • 10. 发明授权
    • Semiconductor laser device
    • 半导体激光器件
    • US08619829B2
    • 2013-12-31
    • US12813235
    • 2010-06-10
    • Yuta YoshidaSachio KarinoTakahiro YokoyamaMakoto NakashimaEiji Takase
    • Yuta YoshidaSachio KarinoTakahiro YokoyamaMakoto NakashimaEiji Takase
    • H01S5/00
    • H01S5/4031H01S5/02276H01S5/0425H01S5/2275
    • The present invention provides a semiconductor laser device including: a plurality of light emitting sections arranged in strip shapes in parallel; a plurality of first electrodes arranged along top faces of the light emitting sections, respectively; an insulating film covering a whole surface of the plurality of first electrodes, and including contact apertures corresponding to the first electrodes, respectively; a plurality of second electrodes arranged in positions different from those of the plurality of light emitting sections, correspondingly to the first electrodes; a plurality of wiring layers arranged on the insulating layer, and electrically connecting the second electrodes and the corresponding first electrodes through the contact apertures, respectively; and a plurality of window regions arranged for the light emitting sections in the insulating film so as to expose the first electrodes, respectively, and including at least two window regions having areas different from each other.
    • 本发明提供一种半导体激光装置,包括:多个发光部分,其平行排列成条状; 分别沿着所述发光部的顶面配置的多个第一电极; 覆盖所述多个第一电极的整个表面的绝缘膜,并且分别包括对应于所述第一电极的接触孔; 与所述多个发光部的位置不同的多个第二电极,对应于所述第一电极; 布置在所述绝缘层上的多个布线层,并分别通过所述接触孔与所述第二电极和所述对应的第一电极电连接; 以及多个窗口区域,其布置成用于绝缘膜中的发光部分,以分别暴露第一电极,并且包括至少两个具有彼此不同区域的窗口区域。