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1. 发明授权

US07779198B2 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories 有权
标题翻译：分页存储器的交错寻址的多个缩写的方法和装置
公开(公告)号：US07779198B2
公开(公告)日：2010-08-17
申请号：US11719926
申请日：2005-11-21
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F12/06
CPC分类号： G11C7/1042 , G06F12/0607 , G11C8/12
摘要： An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B−1) each addressing more than one and less than all of the memory banks. The interleaves are offset (S) from each adjacent other as to address all of the memory banks equally.An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.
摘要翻译：用于寻址多个存储体（12,72）的交错寻址技术使用多个缩写交错（0,1,1,2B-1），每个对每个寻址多于一个且小于所有存储体。交错从每个相邻的另一个偏移（S），以平均地寻址所有存储体。用于存储多个向量的交错存储器的智能存储器包括设置装置（96）为每个向量接收初始地址（B + C + V + NMSK）和间隔数据（D）。寻址逻辑（90）将存储器单元选择（C）与多个向量中的每一个的每个初始和后续地址相关联。小区选择装置（98）使用与每个向量的初始和连续地址的相应一个相关联的存储单元选择（C）访问存储单元（在92中）。

2. 发明申请

US20090043943A1 METHOD AND APPARATUS OF MULTIPLE ABBREVIATIONS OF INTERLEAVED ADDRESSING OF PAGED MEMORIES AND INTELLIGENT MEMORY BANKS THEREFOR 有权
标题翻译： PAGED记忆体和智能记忆体的交互式解决方案的多种缩写的方法和装置
公开(公告)号：US20090043943A1
公开(公告)日：2009-02-12
申请号：US11719926
申请日：2005-11-21
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F12/06
CPC分类号： G11C7/1042 , G06F12/0607 , G11C8/12
摘要： An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B−1) each addressing more than one and less than all of the memory banks. The interleaves are offset (S) from each adjacent other as to address all of the memory banks equally.An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.
摘要翻译：用于寻址多个存储体（12,72）的交错寻址技术使用多个缩写交错（0,1,1,2B-1），每个对每个寻址多于一个且小于所有存储体。交错从每个相邻的另一个偏移（S），以平均地寻址所有存储体。用于存储多个向量的交错存储器的智能存储器包括设置装置（96）为每个向量接收初始地址（B + C + V + NMSK）和间隔数据（D）。寻址逻辑（90）将存储器单元选择（C）与多个向量中的每一个的每个初始和后续地址相关联。小区选择装置（98）使用与每个向量的初始和连续地址的相应一个相关联的存储单元选择（C）访问存储单元（在92中）。

3. 发明授权

US07660967B2 Result data forwarding in parallel vector data processor based on scalar operation issue order 有权
标题翻译：基于标量运算问题顺序的并行向量数据处理器中的结果数据转发
公开(公告)号：US07660967B2
公开(公告)日：2010-02-09
申请号：US12022421
申请日：2008-01-30
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F17/16
CPC分类号： G06F9/30036 , G06F9/3004 , G06F9/3012 , G06F9/30141 , G06F9/3455 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3871 , G06F9/3885 , G06F15/8084
摘要： A computer processor is responsive to successive processing instructions in an issue order to process regular vectors to generate a result vector without use of a cache. At least two architectural registers having input-vector capability are selectively coupled to memory to receive corresponding vector-elements of two vectors and transfer the vector-elements to a selected functional unit. At least one architectural register having output capability is selectively coupled to an output, which in turn is coupled to transfer result vector-elements to the memory. The functional unit performs a function on the vector-elements to generate a respective result-element. The result-elements are transferred to a selected architectural register for processing as operands in performance of further functions by a functional unit, or are transferred to the output for transfer to memory. In either case, the order of the result vector-elements is restored to the issue order of the successive processing instructions.In some embodiments, restore order buffers operate with issue-order codes of result-elements in result registers and architectural registers to restore order to the result vector-elements for output to memory.
摘要翻译：计算机处理器响应于发布顺序中的连续处理指令来处理规则向量以生成结果向量而不使用高速缓存。具有输入向量能力的至少两个架构寄存器选择性地耦合到存储器以接收两个向量的相应向量元素，并将向量元素传送到所选择的功能单元。具有输出能力的至少一个架构寄存器选择性地耦合到输出，输出又被耦合以将结果矢量元件传送到存储器。功能单元对矢量元素执行功能以生成相应的结果元素。结果元素被传送到所选择的架构寄存器，用于作为功能单元执行其他功能的操作数进行处理，或者被传送到输出以传送到存储器。在任一情况下，结果向量元素的顺序被恢复到连续处理指令的发布顺序。在一些实施例中，恢复顺序缓冲器与结果寄存器和架构寄存器中的结果元素的发布顺序代码一起工作，以将结果向量元素的顺序恢复到输出到存储器。

4. 发明申请

US20080189513A1 VECTOR PROCESSING 有权
标题翻译：矢量处理
公开(公告)号：US20080189513A1
公开(公告)日：2008-08-07
申请号：US12022421
申请日：2008-01-30
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/3004 , G06F9/3012 , G06F9/30141 , G06F9/3455 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3871 , G06F9/3885 , G06F15/8084
摘要： A computer processor is responsive to successive processing instructions in an issue order to process regular vectors to generate a result vector without use of a cache. At least two architectural registers having input-vector capability are selectively coupled to memory to receive corresponding vector-elements of two vectors and transfer the vector-elements to a selected functional unit. At least one architectural register having output capability is selectively coupled to an output, which in turn is coupled to transfer result vector-elements to the memory. The functional unit performs a function on the vector-elements to generate a respective result-element. The result-elements are transferred to a selected architectural register for processing as operands in performance of further functions by a functional unit, or are transferred to the output for transfer to memory. In either case, the order of the result vector-elements is restored to the issue order of the successive processing instructions.In some embodiments, restore order buffers operate with issue-order codes of result-elements in result registers and architectural registers to restore order to the result vector-elements for output to memory.
摘要翻译：计算机处理器响应于发布顺序中的连续处理指令来处理规则向量以生成结果向量而不使用高速缓存。具有输入向量能力的至少两个架构寄存器选择性地耦合到存储器以接收两个向量的相应向量元素，并将向量元素传送到所选择的功能单元。具有输出能力的至少一个架构寄存器选择性地耦合到输出，输出又被耦合以将结果矢量元件传送到存储器。功能单元对矢量元素执行功能以生成相应的结果元素。结果元素被传送到所选择的架构寄存器，用于作为功能单元执行其他功能的操作数进行处理，或者被传送到输出以传送到存储器。在任一情况下，结果向量元素的顺序被恢复到连续处理指令的发布顺序。在一些实施例中，恢复顺序缓冲器与结果寄存器和架构寄存器中的结果元素的发布顺序代码一起工作，以将结果向量元素的顺序恢复到输出到存储器。

5. 发明授权

US4296477A Register device for transmission of data having two data ranks one of which receives data only when the other is full 失效
标题翻译：用于传输具有两个数据等级的数据的寄存器装置，其中一个数据仅在另一个数据等级满时才接收数据
公开(公告)号：US4296477A
公开(公告)日：1981-10-20
申请号：US95698
申请日：1979-11-19
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G11C19/00 , G06F5/06 , G06F5/08 , G06F13/38 , H04L25/05 , G06F13/00
CPC分类号： G06F5/08 , H04L25/05
摘要： A register data transmission system has a plurality of register devices connected in series to form a data transmission link between a sending device and a receiving device. This register system can function between independent synchronous operating units of a computer such as a pair of data buffers. As data is transmitted, the individual register devices absorb the data as compactly as necessary within limits, to form the data path. Each register device has two data registers and two control flip-flops. The two data registers are the primary and secondary data rank registers. The secondary data rank register only receives data when the primary data rank register cannot receive data. The two control flip-flops are the primary and secondary full-bit flip-flops. Each register device has a clock control. In operation, data travels from the sending device through each register device to the receiving device while a control signal travels from the receiving device to the sending device. Data traveling through the register devices in a transmission path has a pattern analogous to a rippling effect because the timing sequence for the Hold signal from the receiving device travels in a reverse direction through the control flip-flops of the register devices to push the data along in stages. This rippling occurs as a result of each register device holding data in secondary data ranks when the receiving device stops data flow and while the sending device is shutting off.
摘要翻译：寄存器数据传输系统具有串联连接的多个寄存器装置，以在发送装置和接收装置之间形成数据传输链路。该寄存器系统可以在诸如一对数据缓冲器的计算机的独立同步操作单元之间工作。随着数据的传输，各个寄存器件在限制内按需要紧凑地吸收数据，形成数据路径。每个寄存器都有两个数据寄存器和两个控制触发器。两个数据寄存器是主要和次要数据等级寄存器。次级数据等级寄存器仅在主数据等级寄存器不能接收数据时才接收数据。两个控制触发器是主要和次要的全位触发器。每个寄存器都有一个时钟控制。在操作中，当控制信号从接收设备传送到发送设备时，数据从发送设备通过每个寄存器设备传送到接收设备。在传输路径中通过寄存器设备传输的数据具有类似于波动效应的模式，因为来自接收设备的保持信号的定时序列通过寄存器设备的控制触发器沿相反方向行进，以推送数据分阶段当接收设备停止数据流并且发送设备正在关闭时，由于每个寄存器设备保持次级数据中的数据排列的结果发生这种波动。

6. 发明授权

US08190809B2 Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines 有权
标题翻译：分流交织用于访问多个存储体，特别是具有部分访问的包含高速缓存行数据的单元的单元
公开(公告)号：US08190809B2
公开(公告)日：2012-05-29
申请号：US12698719
申请日：2010-02-02
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), −Q+mod(2A,Q), ±1 or ±prime to , where −
摘要翻译：银行选择装置具有多个可寻址位置和彼此相关的多个存储位置，使得每个存储位置与多个可寻址位置相关联，并且每个可寻址位置与一个存储位置相关联。每个存储位置都包含相应的存储区选择。可寻址位置和存储位置被分组为交织模式，使得对于每个模式，存在布置在L个顺序循环中的Q个存储位置和2A个可寻址位置，每个循环包含Q个可顺序寻址的位置，以及包含R个可顺序寻址的位置的余数循环，其中L ·Q + R = 2A。分流器为每个交织定义非零偏移，使得每个交织开始于不同的存储体选择，并且所有交织的完全旋转对每个存储器组寻址相同次数。分流器（S）可以被选择为mod（2A，Q），-Q + mod（2A，Q），±1或±素数，其中 -

7. 发明授权

US08074010B2 Intelligent memory banks for storing vectors 有权
标题翻译：用于存储向量的智能存储体
公开(公告)号：US08074010B2
公开(公告)日：2011-12-06
申请号：US12831400
申请日：2010-07-07
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F12/00
CPC分类号： G11C7/1042 , G06F12/0607 , G11C8/12
摘要： An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.
摘要翻译：用于存储多个向量的交错存储器的智能存储器包括设置装置（96）为每个向量接收初始地址（B + C + V + NMSK）和间隔数据（D）。寻址逻辑（90）将存储器单元选择（C）与多个向量中的每一个的每个初始和后续地址相关联。小区选择装置（98）使用与每个向量的初始和连续地址的相应一个相关联的存储单元选择（C）访问存储单元（在92中）。

8. 发明申请

US20100312945A1 INTELLIGENT MEMORY BANKS FOR STORING VECTORS 有权
标题翻译：用于存储向量的智能存储器
公开(公告)号：US20100312945A1
公开(公告)日：2010-12-09
申请号：US12831400
申请日：2010-07-07
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F12/00 , G06F7/50
CPC分类号： G11C7/1042 , G06F12/0607 , G11C8/12
摘要： An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.
摘要翻译：用于存储多个向量的交错存储器的智能存储器包括设置装置（96）为每个向量接收初始地址（B + C + V + NMSK）和间隔数据（D）。寻址逻辑（90）将存储器单元选择（C）与多个向量中的每一个的每个初始和后续地址相关联。小区选择装置（98）使用与每个向量的初始和连续地址的相应一个相关联的存储单元选择（C）访问存储单元（在92中）。

9. 发明申请

US20100138587A1 SHUNTED INTERLEAVE FOR ACCESSING PLURAL MEMORY BANKS, PARTICULARLY THOSE HAVING PARTIALLY ACCESSED CELLS CONTAINING DATA FOR CACHE LINES 有权
标题翻译：用于访问多个存储器银行的分流交换机，特别是具有包含用于缓存线路的数据的部分接入电池
公开(公告)号：US20100138587A1
公开(公告)日：2010-06-03
申请号：US12698719
申请日：2010-02-02
申请人： Maurice L. Hutson
发明人： Maurice L. Hutson
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G06F12/0607
摘要： A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), −Q+mod(2A,Q), ±1 or ±prime to , where −
摘要翻译：银行选择装置具有多个可寻址位置和彼此相关的多个存储位置，使得每个存储位置与多个可寻址位置相关联，并且每个可寻址位置与一个存储位置相关联。每个存储位置都包含相应的存储区选择。可寻址位置和存储位置被分组成交织模式，使得对于每个模式，存在布置在L个顺序循环中的Q个存储位置和2A个可寻址位置，每个循环包含Q个可顺序寻址的位置，以及包含R个可顺序寻址的位置的余数循环，其中L ·Q + R = 2A。分流器为每个交织定义非零偏移，使得每个交织开始于不同的存储体选择，并且所有交织的完全旋转对每个存储器组寻址相同次数。分流器（S）可以被选择为mod（2A，Q），-Q + mod（2A，Q），±1或±素数，其中 -

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