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1. 发明申请

US20200234737A1 LEAKAGE CURRENT REDUCTION IN A DUAL RAIL DEVICE 审中-公开
公开(公告)号：US20200234737A1
公开(公告)日：2020-07-23
申请号：US16253210
申请日：2019-01-21
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Chaoqun Liu , Yipin Wu , Soh Chee Keong
IPC分类号： G11C5/14 , G11C11/417
摘要： A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level which is lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.

2. 发明授权

US11004480B2 Leakage current reduction in a dual rail device 有权
公开(公告)号：US11004480B2
公开(公告)日：2021-05-11
申请号：US16253210
申请日：2019-01-21
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Chaoqun Liu , Yipin Wu , Soh Chee Keong
IPC分类号： G11C7/00 , G11C5/14 , G11C11/417
摘要： A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level which is lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.

3. 发明申请

US20180158823A1 Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture 审中-公开
公开(公告)号：US20180158823A1
公开(公告)日：2018-06-07
申请号：US15866407
申请日：2018-01-09
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Navienkumar Ramachandran Arumugam
IPC分类号： H01L27/092 , H01L27/02 , H01L27/118 , H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2027/11851
摘要： Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. An MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

4. 发明授权

US11640834B2 Voltage droop reduction with a secondary power supply 有权
公开(公告)号：US11640834B2
公开(公告)日：2023-05-02
申请号：US17079462
申请日：2020-10-24
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Yang Bai , Chaoqun Liu , Yipin Wu , Chih-Hung Tai
IPC分类号： G11C5/14 , G05F1/56 , H03K5/01
摘要： A droop reduction circuit on a die includes a voltage detector circuit to detect voltage droop in a supply voltage received by a first load. The droop reduction circuit further includes a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop. Each of the PSH banks includes at least one power switch having an input terminal, a gate terminal, and an output terminal. The input terminal is to receive a secondary voltage, which is higher than the supply voltage and is also received by a second load on the die. The gate terminal is to receive a drive signal from the driver controller, and the output terminal is to pull up the voltage droop in the supply voltage.

5. 发明授权

US09813047B2 Standby mode state retention logic circuits 有权
公开(公告)号：US09813047B2
公开(公告)日：2017-11-07
申请号：US14984020
申请日：2015-12-30
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal
IPC分类号： H03K3/356 , H03K3/012 , H03K3/037
CPC分类号： H03K3/356008 , H03K3/012 , H03K3/0375
摘要： A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an active high retention signal input and an active low reset input. In another example, the circuit is a retention flip-flop that has an active low retention signal input and an active low reset input. In a multi-bit retention register example, one common clock and reset signal generation logic circuit drives multiple pairs of latches. Each retention mode logic circuit described has a low transistor count, is implemented with a single N-well, exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.

6. 发明申请

US20160111424A1 Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture 有权
标题翻译：基于永久性N阱结构的多电压互补金属氧化物半导体集成电路
公开(公告)号：US20160111424A1
公开(公告)日：2016-04-21
申请号：US14983796
申请日：2015-12-30
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Navienkumar Ramachandran Arumugam
IPC分类号： H01L27/092 , G06F17/50 , H01L23/528
CPC分类号： H01L27/0921 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2027/11851
摘要： Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.
摘要翻译：描述了基于永久在线N阱架构的多电压（MV）互补金属氧化物半导体（CMOS）集成电路（IC）的示例。 MV CMOS IC可以包括第一CMOS电池，第二CMOS电池，N阱和永久在线抽头。每个第一CMOS单元可以具有被配置为接收本地电源电压的电源端子和被配置为接收全局电源电压的N阱（NW）端子。第二CMOS单元可以包括总是在CMOS单元。每个第二CMOS单元可以具有被配置为接收全局电源电压的供电端子，以及被配置为接收全局电源电压的NW端子。可以在一个或多个N阱的第一N阱中形成第二CMOS单元中的至少一个的NW端子和至少一个第一CMOS单元的NW端子。

7. 发明申请

US20220130432A1 VOLTAGE DROOP REDUCTION WITH A SECONDARY POWER SUPPLY 有权
公开(公告)号：US20220130432A1
公开(公告)日：2022-04-28
申请号：US17079462
申请日：2020-10-24
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Yang Bai , Chaoqun Liu , Yipin Wu , Chih-Hung Tai
IPC分类号： G11C5/14 , G05F1/56 , H03K5/01
摘要： A droop reduction circuit on a die includes a voltage detector circuit to detect voltage droop in a supply voltage received by a first load. The droop reduction circuit further includes a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop. Each of the PSH banks includes at least one power switch having an input terminal, a gate terminal, and an output terminal. The input terminal is to receive a secondary voltage, which is higher than the supply voltage and is also received by a second load on the die. The gate terminal is to receive a drive signal from the driver controller, and the output terminal is to pull up the voltage droop in the supply voltage.

8. 发明授权

US09905560B2 Multi-voltage complementary metal oxide semiconductor integrated circuits based on always-on N-well architecture 有权
公开(公告)号：US09905560B2
公开(公告)日：2018-02-27
申请号：US14983796
申请日：2015-12-30
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal , Navienkumar Ramachandran Arumugam
IPC分类号： H01L23/528 , H01L27/092 , G06F17/50 , H01L27/02 , H01L27/118 , H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2027/11851
摘要： Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

9. 发明申请

US20160301396A1 Standby Mode State Retention Logic Circuits 有权
标题翻译：待机模式状态保持逻辑电路
公开(公告)号：US20160301396A1
公开(公告)日：2016-10-13
申请号：US14984020
申请日：2015-12-30
申请人： MediaTek Singapore Pte. Ltd.
发明人： Senthilkumar Jayapal
IPC分类号： H03K3/356
CPC分类号： H03K3/356008 , H03K3/012 , H03K3/0375
摘要： A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an active high retention signal input and an active low reset input. In another example, the circuit is a retention flip-flop that has an active low retention signal input and an active low reset input. In a multi-bit retention register example, one common clock and reset signal generation logic circuit drives multiple pairs of latches. Each retention mode logic circuit described has a low transistor count, is implemented with a single N-well, exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.
摘要翻译：保持模式顺序逻辑电路没有气球闩锁，并且其所有P沟道晶体管都设置在单个N阱中。在一个示例中，电路是具有有效的高保持信号输入和有效低复位输入的保持触发器。在另一个例子中，该电路是保持触发器，其具有有源低保持信号输入和有效低复位输入。在多位保持寄存器示例中，一个公共时钟和复位信号产生逻辑电路驱动多对锁存器。所描述的每个保持模式逻辑电路具有低的晶体管数量，用单个N阱实现，具有低保持模式功率消耗，不响应于保持模式中的复位信号，并且当出现时具有快速的响应时间保留模式操作。

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